Datasheet

WCLK
BCLK
DOUT
DIN
t
d(DO-WS)
t
d(DO-BCLK)
t
S(DI)
t
h(DI)
t
d(WS)
TLV320AIC3204
www.ti.com SLOS602B –SEPTEMBER 2008–REVISED OCTOBER 2012
Interface Timing
Typical Timing Characteristics — Audio Data Serial Interface Timing (I
2
S)
All specifications at 25°C, DVdd = 1.8V
Figure 3. I
2
S LJF and RJF Timing in Master Mode
Table 2. I
2
S LJF and RJF Timing in Master Mode (see Figure 3)
PARAMETER IOVDD=1.8V IOVDD=3.3V UNITS
MIN MAX MIN MAX
t
d(WS)
WCLK delay 30 20 ns
t
d(DO-WS)
WCLK to DOUT delay (For LJF Mode only) 20 20 ns
t
d(DO-BCLK)
BCLK to DOUT delay 22 20 ns
t
s(DI)
DIN setup 8 8 ns
t
h(DI)
DIN hold 8 8 ns
t
r
Rise time 24 12 ns
t
f
Fall time 24 12 ns
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