Datasheet

TLV320AIC31
www.ti.com ............................................................................................................................................. SLAS497C – AUGUST 2006 – REVISED DECEMBER 2008
Page 0 / Register 12: Audio Codec Digital Filter Control Register
BIT READ/ RESET DESCRIPTION
WRITE VALUE
D7 – D6 R/W 00 Left ADC High-pass Filter Control
00: Left ADC High-pass filter disabled
01: Left ADC High-pass filter – 3-dB frequency = 0.0045 × ADC F
S
10: Left ADC High-pass filter – 3-dB frequency = 0.0125 × ADC F
S
11: Left ADC High-pass filter – 3-dB frequency = 0.025 × ADC F
S
D5 – D4 R/W 00 Right ADC High-pass Filter Control
00: Right ADC High-pass filter disabled
01: Right ADC High-pass filter – 3-dB frequency = 0.0045 × ADC F
S
10: Right ADC High-pass filter – 3-dB frequency = 0.0125 × ADC F
S
11: Right ADC High-pass filter – 3-dB frequency = 0.025 × ADC F
S
D3 R/W 0 Left DAC Digital Effects Filter Control
0: Left DAC digital effects filter disabled (bypassed)
1: Left DAC digital effects filter enabled
D2 R/W 0 Left DAC De-emphasis Filter Control
0: Left DAC de-emphasis filter disabled (bypassed)
1: Left DAC de-emphasis filter enabled
D1 R/W 0 Right DAC Digital Effects Filter Control
0: Right DAC digital effects filter disabled (bypassed)
1: Right DAC digital effects filter enabled
D0 R/W 0 Right DAC De-emphasis Filter Control
0: Right DAC de-emphasis filter disabled (bypassed)
1: Right DAC de-emphasis filter enabled
Page 0 / Register 13: Reserved
BIT READ/ RESET DESCRIPTION
WRITE VALUE
D7 – D0 R/W 00000000 Reserved. Write only '00000000' to this register.
Page 0 / Register 14: Headset Configuration Register
BIT READ/ RESET DESCRIPTION
WRITE VALUE
D7 R/W 0 Driver Capacitive Coupling
0: Programs high-power outputs for capless driver configuration
1: Programs high-power outputs for ac-coupled driver configuration
D6
(1)
R/W 0 Stereo Output Driver Configuration A
Note: do not set bits D6 and D3 both high at the same time.
0: A stereo fully-differential output configuration is not being used
1: A stereo fully-differential output configuration is being used
D5 – D4 R 00 Reserved. Write only '00' to these bits.
D3
(1)
R/W 0 Stereo Output Driver Configuration B
Note: do not set bits D6 and D3 both high at the same time.
0: A stereo pseudo-differential output configuration is not being used
1: A stereo pseudo-differential output configuration is being used
D2 – D0 R 000 Reserved. Write only 0s to these bits.
(1) Do not set D6 and D3 to 1 simultaneously
Page 0 / Register 15: Left ADC PGA Gain Control Register
BIT READ/ RESET DESCRIPTION
WRITE VALUE
D7 R/W 1 Left ADC PGA Mute
0: The left ADC PGA is not muted
1: The left ADC PGA is muted
Copyright © 2006 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 43
Product Folder Link(s): TLV320AIC31