Datasheet
TLV320AIC3106
SLAS509E – DECEMBER 2006 – REVISED DECEMBER 2008 ........................................................................................................................................
www.ti.com
f
S(ref)
= (PLLCLK_IN × K × R) / (2048 × P), where
P = 1, 2, 3, … , 8
R = 1, 2, … , 16
K = J.D
J = 1, 2, 3, … , 63
D = 0000, 0001, 0002, 0003, … , 9998, 9999
PLLCLK_IN can be MCLK or BCLK, selected by Page 0, register 102, bits D5-D4
P, R, J, and D are register programmable. J is the integer portion of K (the numbers to the left of the decimal
point), while D is the fractional portion of K (the numbers to the right of the decimal point, assuming four digits of
precision).
Examples:
If K = 8.5, then J = 8, D = 5000
If K = 7.12, then J = 7, D = 1200
If K = 14.03, then J = 14, D = 0300
If K = 6.0004, then J = 6, D = 0004
When the PLL is enabled and D = 0000, the following conditions must be satisfied to meet specified
performance:
2 MHz ≤ ( PLLCLK_IN / P ) ≤ 20 MHz
80 MHz ≤ (PLLCLK _IN × K × R / P ) ≤ 110 MHz
4 ≤ J ≤ 55
When the PLL is enabled and D ≠ 0000, the following conditions must be satisfied to meet specified performance:
10 MHz ≤ PLLCLK _IN / P ≤ 20 MHz
80 MHz ≤ PLLCLK _IN × K × R / P ≤ 110 MHz
4 ≤ J ≤ 11
R = 1
Example:
MCLK = 12 MHz and f
S(ref)
= 44.1 kHz
Select P = 1, R = 1, K = 7.5264, which results in J = 7, D = 5264
Example:
MCLK = 12 MHz and f
S(ref)
= 48 kHz
Select P = 1, R = 1, K = 8.192, which results in J = 8, D = 1920
The table below lists several example cases of typical MCLK rates and how to program the PLL to achieve f
S(ref)
= 44.1 kHz or 48 kHz.
f
S(ref)
= 44.1 kHz
MCLK (MHz) P R J D ACHIEVED f
S(ref)
% ERROR
2.8224 1 1 32 0 44100.00 0.0000
5.6448 1 1 16 0 44100.00 0.0000
12.0 1 1 7 5264 44100.00 0.0000
13.0 1 1 6 9474 44099.71 – 0.0007
16.0 1 1 5 6448 44100.00 0.0000
19.2 1 1 4 7040 44100.00 0.0000
19.68 1 1 4 5893 44100.30 0.0007
48.0 4 1 7 5264 44100.00 0.0000
f
S(ref)
= 48 kHz
MCLK (MHz) P R J D ACHIEVED f
S(ref)
% ERROR
2.048 1 1 48 0 48000.00 0.0000
3.072 1 1 32 0 48000.00 0.0000
4.096 1 1 24 0 48000.00 0.0000
6.144 1 1 16 0 48000.00 0.0000
30 Submit Documentation Feedback Copyright © 2006 – 2008, Texas Instruments Incorporated
Product Folder Link(s): TLV320AIC3106