Datasheet
TLV320AIC3104
SLAS510C –FEBRUARY 2007–REVISED DECEMBER 2010
www.ti.com
Table 45. Page 0/Register 70: PGA_R to HPRCOM Volume Control Register
BIT READ/ RESET DESCRIPTION
WRITE VALUE
D7 R/W 0 PGA_R Output Routing Control
0: PGA_R is not routed to HPRCOM.
1: PGA_R is routed to HPRCOM.
D6–D0 R/W 000 0000 PGA_R to HPRCOM Analog Volume Control
For 7-bit register settings versus analog gain values, see Table 19.
Table 46. Page 0/Register 71: DAC_R1 to HPRCOM Volume Control Register
BIT READ/ RESET DESCRIPTION
WRITE VALUE
D7 R/W 0 DAC_R1 Output Routing Control
0: DAC_R1 is not routed to HPRCOM.
1: DAC_R1 is routed to HPRCOM.
D6–D0 R/W 000 0000 DAC_R1 to HPRCOM Analog Volume Control
For 7-bit register settings versus analog gain values, see Table 19.
Table 47. Page 0/Register 72: HPRCOM Output Level Control Register
BIT READ/ RESET DESCRIPTION
WRITE VALUE
D7–D4 R/W 0000 HPRCOM Output Level Control
0000: Output level control = 0 dB
0001: Output level control = 1 dB
0010: Output level control = 2 dB
...
1000: Output level control = 8 dB
1001: Output level control = 9 dB
1010–1111: Reserved. Do not write these sequences to these register bits.
D3 R/W 0 HPRCOM Mute
0: HPRCOM is muted.
1: HPRCOM is not muted.
D2 R/W 1 HPRCOM Power-Down Drive Control
0: HPRCOM is weakly driven to a common mode when powered down.
1: HPRCOM is high-impedance when powered down.
D1 R 1 HPRCOM Volume Control Status
0: All programmed gains to HPRCOM have been applied.
1: Not all programmed gains to HPRCOM have been applied yet.
D0 R/W 0 HPRCOM Power Control
0: HPRCOM is not fully powered up.
1: HPRCOM is fully powered up.
Table 48. Page 0/Registers 73–78: Reserved
BIT READ/ RESET DESCRIPTION
WRITE VALUE
D7–D0 R 0000 0000 Reserved. Do not write to these registers.
Table 49. Page 0/Register 79: Reserved
BIT READ/ RESET DESCRIPTION
WRITE VALUE
D7–D0 R 0000 0010 Reserved. Do not write to this register.
Table 50. Page 0/Register 80: Reserved
BIT READ/ RESET DESCRIPTION
WRITE VALUE
D7–D0 R 0000 0000 Reserved. Do not write to this register.
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