Datasheet

T0146-02
WCLK
BCLK
SDOUT
SDIN
t (WS)
h
t (WS)
h
t (BCLK)
L
t (DO-BCLK)
d
t (DI)
S
t (BCLK)
H
t (DI)
h
t (WS)
S
t (WS)
S
TLV320AIC3104
SLAS510C –FEBRUARY 2007–REVISED DECEMBER 2010 www.ti.com
All specifications at 25°C, DVDD = 1.8 V.
IOVDD = 1.1 V IOVDD = 3.3 V
PARAMETER UNIT
MIN MAX MIN MAX
t
H
(BCLK) BCLK high period 70 35 ns
t
L
(BCLK) BCLK low period 70 35 ns
t
s
(WS) ADWS/WCLK setup time 10 8 ns
t
h
(WS) ADWS/WCLK hold time 10 8 ns
t
d
(DO-BCLK) BCLK to DOUT delay time 50 20 ns
t
s
(DI) DIN setup time 10 6 ns
t
h
(DI) DIN hold time 10 6 ns
t
r
Rise time 8 4 ns
t
f
Fall time 8 4 ns
NOTE: All timing specifications are measured at characterization but not tested at final test.
Figure 4. DSP Timing in Slave Mode
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