Datasheet

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Control Register Content Description
TLV320AIC20, TLV320AIC21
TLV320AIC24, TLV320AIC25
TLV320AIC20K, TLV320AIC24K
SLAS363D – MARCH 2002 – REVISED APRIL 2005
Control Register 1
(1)
D7 D6 D5 D4 D3 D2 D1 D0
ADOVF CX IIR DAOVF BIASV ALB DLB DAC16
R R/W/S R/W R R/W/S R/W R/W R/W/S
(1) NOTE: R = Read, W = Write, S = Shadowed
Control Register 1 Bit Summary
RESET
BIT NAME FUNCTION
VALUE
ADC over flow. This bit indicates whether the ADC is overflow.
D7 ADOVF 0 ADOVF = 0 No overflow
ADOVF = 1 A/D is overflow.
Continuous data transfer mode. This bit selects between programming mode and continuous data transfer
mode.
D6 CX 0
CX = 0 Programming mode
CX = 1 Continuous data transfer mode
IIR Filter. This bit selects between FIR and IIR for decimation/interpolation low-pass filter.
D5 IIR 0 IIR = 0 FIR filter is selected
IIR = 1 IIR filter is selected.
DAC over flow. This bit indicates whether the DAC is overflow
D4 DAOVF 0 DAOVF = 0 No overflow
DAOVF = 1 DAC is overflow
Bias voltage. This bit selects the output voltage for BIAS pin
BIASV = 0
D3 BIASV 0 BIAS pin = 1.35 V
BIASV = 1
BIAS pin = 2.35 V
Analog loop back
D2 ALB 0 ALB = 0 Analog loopback disabled
ALB = 1 Analog loopback enabled
Digital loop back
D1 DLB 0 DLB = 0 Digital loopback disabled
DLB = 1 Digital loopback enabled
DAC 16-bit data format. This bit applies to the continuous data transfer mode only to enable the 16-bit data
format for DAC input.DAC16 = 0 DAC input data length is 15 bits. Writing a 1 to the LSB of the DAC input to
D0 DAC16 0
switch from continuous data transfer mode to programming mode.
DAC16 = 1 DAC input data length is 16 bit.
Control Register 2
(1)
D7 D6 D5 D4 D3 D2 D1 D0
TURBO DIFBP I
2
C6 I
2
C5 I
2
C4 GPO HPC
R/W/S R/W/S R/W/S R/W/S R/W/S R/W/S R/W/S R/W/S
(1) NOTE: R = Read, W = Write, S = Shadowed
Control Register 2 Bit Summary
RESET
BIT NAME FUNCTION
VALUE
Turbo mode. This bit is used to set the SCLK rate.
D7 TURBO 0 TURBO = 0 SCLK = (16 × FS × number of device × mode)
TURBO = 1 SCLK = MCLK/P (P is determined in register 4)
Decimation/interpolation filter bypass. This bit is used to bypass both decimation and interpolation filters.
D6 DIFBP 0 DIFBP = 0 Decimation/interpolation filters are operated.
DIFBP = 1 Decimation/interpolation filters are bypassed.
I
2
C device address. These three bits are programmable to define three MSBs of the I
2
C device address
D5-D3 I
2
Cx 100 (reset value is 100). These three bits are combined with the 4-bit SMARTDM device address to form 7-bit
I
2
C device address.
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