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SCLK
FS
DIN/
DOUT
0 1 2 n-1n-2n-3 0 1 2 n-1n-2n-3
Data Frame / Sample 1
NOTE: n is the total number of AIC12s in the cascade
16 SCLKs Per Time Slot
Data Frame / Sample 2
Slot
Number
Master Slave
n-2
Slave
1
Slave
2
Slave
n-3
Slave
0
Master Slave
n-2
Slave
n-3
Slave
2
Slave
1
Slave
0
Turbo Operation (SCLK)
TLV320AIC12, TLV320AIC13
TLV320AIC14, TLV320AIC15
TLV320AIC12K, TLV320AIC14K
SLWS115E – OCTOBER 2001 – REVISED JANUARY 2007
Figure 37. Standard Operation/Continuous Data Transfer Mode: Master-Slave Cascade Timing
Setting TURBO = 1 (bit D7) in control register 2 enables the turbo mode that requires the following condition to
be met:
• For master with SCLK as output, M × N > #Devices × mode
Where:
• M, N, and P are clock divider values defined in the control register 4. #Device is the number of the device in
cascade. Mode is equal to 1 for continuous data transfer mode and 2 for programming mode.
• For slave, SCLK is the input with max allowable speed of 25 MHz (no condition is required).
• The number of SCLKs per FS can be ≥ (16 × mode).
The turbo operation is useful for applications that require more bandwidth for multitasking processing per
sampling period. In the turbo mode (see Figure 38 ), the FSs frequency is always the device's sampling
frequency but the SCLK is running at much higher speed than that described in Section 3.6.1. The output SCLK
frequency is equal to (MCLK/P) in master mode and up to a maximum speed of 25 MHz for both master and
slave AIC1x. The data/control frame is still 16-SCLK long and the FS is one-SCLK pulse. If the 'AIC1x is in slave
mode, and the device is not set to turbo mode, only the first FS is used to synchronize the data transfer. The
'AIC1x ignores all subsequent FS signals and utilizes an internally generated FS. However, if the 'AIC1x is set to
turbo mode while in slave mode, then the data transfer synchronizes on every FS signal. Therefore, it is
recommended that if the 'AIC1x is set to slave mode, then turbo mode is used. Also note that in turbo mode, it is
recommended that SCLK be a multiple of 32 x FS
36
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