Datasheet

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Power Management
Software Power-Down
Hardware Power-Down
Host Port Interface
TLV320AIC12, TLV320AIC13
TLV320AIC14, TLV320AIC15
TLV320AIC12K, TLV320AIC14K
SLWS115E – OCTOBER 2001 – REVISED JANUARY 2007
To calculate the channel address, during the first 64 MCLKs, the device counts the number of clocks between
ACD starting (reset) and the FSD going high. During the next 64 MCLKs, the device counts the number of
clocks till FS is pulled low. The sum total of the counts in the first phase and the second phase is the number of
devices in the channel.
For a cascaded system, the rise time of H/W RESET needs to be less than the MCLK period and should satisfy
setup time requirement of 2 ns with respect to MCLK rise-edge. In stand-alone-slave mode SCLK must be
running during RESET. If more than one codec is cascaded, RESET must be synchronized to MCLK.
Additionally, all devices must see the same edge of MCLK within a window of 0.5 ns The reset signal need not
be synchronized with MCLK when the codec is in stand-alone master or slave configuration.
Most of the device (all except the digital interface) enters the power-down mode when D7 and D6, in control
register 3, are set to 1. When the PWRDN pin is low, the entire device is powered down. In either case, register
contents are preserved.
The amount of power drawn during software power down is higher than during a hardware power down because
of the current required to keep the digital interface active. Additional differences between software and hardware
power-down modes are detailed in the following paragraphs.
Data bits D7 and D6 of control register 3 are used by TLV320AIC1x to turn on or off the software power-down
mode, which takes effect in the next frame FS. The ADC and DAC can be powered down individually. In the
software power-down, the digital interface circuit is still active while the internal ADC and DAC channel and
differential outputs OUTPx and OUTMx are disabled, and DOUT is put in 3-state in the data frame only. Register
data in the control frame is still accepted via DIN, but data in the data frame is ignored. The device returns to
normal operation when D7 and D6 of control register 3 are reset.
The TLV320AIC1x requires the PWRDN signal to be synchronized with MCLK. When PWRDN is held low, the
device enters hardware power-down mode. In this state, the internal clock control circuit and the differential
outputs are disabled. All other digital I/Os are disabled and DIN cannot accept any data input. The device can
only be returned to normal operation by holding PWRDN high. Getting out of the power-down mode (i.e. bringing
PWRDN from low to high state) requires that the low-to-high transition of PWRDN be synchronous to the rising
edge of MCLK. If there is no need for the hardware power-down mode feature of the device, the PWRDN pin
must be tied high.
The host port uses a 2-wire serial interface (SCL, SDA) to program the AIC1x's six control registers and
selectable protocol between S
2
C mode and I
2
C mode. The S
2
C is a write-only mode and the I
2
C is a read-write
mode selected by setting the bits D1 and D0 of control register 2 to 00 or 01. If the host interface is not needed
the two pins of SCL and SDA can be programmed to become general-purpose I/Os by setting the bits D1 and
D0 of control register 2 to 10 or 11. If selected to be used as I/O pins, the SDA and SCL pins become output
and input pins respectively, determined by D1 and D0.
Both S
2
C and I
2
C require a SMARTDM device address to communicate with the AIC1x. One of SMARTDMs
advanced features is the automatic cascade detection (ACD) that enables SMARTDM to automatically detect
the total number of codecs in the serial connection and use this information to assign each codec a distinct
SMARTDM device address. Table 1 lists device addresses assigned to each codec in the cascade by the
SMARTDM. The master always has the highest position in the cascade. For example, if there is a total of 8
codecs in the cascade (i.e., one master and 7 slaves), then the device addresses in row 8 are used in which the
master is codec 7 with a device address of 0111.
Table 1. SMARTDM Device Addresses
TOTAL CODEC POSITION IN CASCADE
CODECS
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 0000
27
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