Datasheet
SLOS186C − FEBRUARY 1997 − REVISED AUGUST 2006
39
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
driving large capacitive loads
The TLV226x is designed to drive larger capacitive loads than most CMOS operational amplifiers. Figure 51
and Figure 52 illustrate its ability to drive loads greater than 400 pF while maintaining good gain and phase
margins (R
null
= 0).
A smaller series resistor (R
null
) at the output of the device (see Figure 61) improves the gain and phase margins
when driving large capacitive loads. Figure 51 and Figure 52 show the effects of adding series resistances of
10 Ω, 20 Ω, 50 Ω, and 100 Ω. The addition of this series resistor has two effects: the first is that it adds a zero
to the transfer function and the second is that it reduces the frequency of the pole associated with the output
load in the transfer function.
The zero introduced to the transfer function is equal to the series resistance times the load capacitance. To
calculate the improvement in phase margin, equation (1) can be used.
∆θ
m1
+ tan
–1
ǒ
2 ×π×UGBW × R
null
× C
L
Ǔ
∆θ
m1
+ improvement in phase margin
UGBW + unity-gain bandwidth frequency
R
null
+ output series resistance
C
L
+ load capacitance
(1)
Where :
The unity-gain bandwidth (UGBW) frequency decreases as the capacitive load increases (see Figure 53). To
use equation 1, UGBW must be approximated from Figure 53.
Using equation 1 alone overestimates the improvement in phase margin as illustrated in Figure 59. The
overestimation is caused by the decrease in the frequency of the pole associated with the load, providing
additional phase shift and reducing the overall improvement in phase margin. The pole associated with the load
is reduced by the factor calculated in equation 2.
F +
1
1 ) g
m
×
R
null
F + factor reducing frequency of pole
g
m
+ small-signal output transconductance (typically 4.83 × 10
–3
mhos)
R
null
+ output series resistance
(2)
Where :
For the TLV226x, the pole associated with the load is typically 7 MHz with 100-pF load capacitance. This value
varies inversely with C
L
: at C
L
= 10 pF, use 70 MHz, at C
L
= 1000 pF, use 700 kHz, and so on.
Reducing the pole associated with the load introduces phase shift, thereby reducing phase margin. This results
in an error in the increase in phase margin expected by considering the zero alone (equation 1). Equation 3
approximates the reduction in phase margin due to the movement of the pole associated with the load. The
result of this equation can be subtracted from the result of the equation 1 to better approximate the improvement
in phase margin.