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   

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SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D Output Swing Includes Both Supply Rails

D Low Noise . . . 19 nV/√Hz Typ at f = 1 kHz

D Low Input Bias Current ...1 pA Typ

D Fully Specified for Both Single-Supply and

Split-Supply Operation

D Very Low Power ...34 µA Per Channel Typ

D Common-Mode Input Voltage Range

Includes Negative Rail

D Low Input Offset Voltage

850 µV Max at T

= 25°C

D Wide Supply Voltage Range

2.7 V to 8 V

D Macromodel Included

D Available in Q-Temp Automotive

HighRel Automotive Applications

Configuration Control / Print Support

Qualification to Automotive Standards

description

The TLV2252 and TLV2254 are dual and

quadruple low-voltage operational amplifiers from

Texas Instruments. Both devices exhibit rail-to-rail

output performance for increased dynamic range

in single- or split-supply applications. The

TLV225x family consumes only 34 µA of supply

current per channel. This micropower operation

makes them good choices for battery-powered

applications. This family is fully characterized at

3 V and 5 V and is optimized for low-voltage

applications. The noise performance has been

dramatically improved over previous generations

of CMOS amplifiers. The TLV225x has a noise

level of 19 nV/√Hz

at 1kHz, four times lower than

competitive micropower solutions.

The TLV225x, exhibiting high input impedance

and low noise, are excellent for small-signal

conditioning for high-impedance sources, such as

piezoelectric transducers. Because of the micro-

power dissipation levels combined with 3-V

operation, these devices work well in hand-held

monitoring and remote-sensing applications. In

addition, the rail-to-rail output feature with single or split supplies makes this family a great choice when

interfacing with analog-to-digital converters (ADCs). For precision applications, the TLV225xA family is

available and has a maximum input offset voltage of 850 µV.

The TLV2252/4 also make great upgrades to the TLV2322/4 in standard designs. They offer increased output

dynamic range, lower noise voltage, and lower input offset voltage. This enhanced feature set allows them to

be used in a wider range of applications. For applications that require higher output drive and wider input voltage

range, see the TLV2432 and TLV2442 devices. If your design requires single amplifiers, please see the

TLV2211/21/31 family. These devices are single rail-to-rail operational amplifiers in the SOT-23 package. Their

small size and low power consumption, make them ideal for high density, battery-powered equipment.

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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Advanced LinCMOS is a trademark of Texas Instruments.

Figure 1

− High-Level Output Voltage − V

HIGH-LEVEL OUTPUT VOLTAGE

HIGH-LEVEL OUTPUT CURRENT

| I

| − High-Level Output Current − µA

1.5

0 200 400

2.5

600 800

= 25°C

= 85°C

0.5

= 125°C

= 3 V

= −40°C

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Summary of content (61 pages)

PAGE 1
 SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006 D D D D D D Output Swing Includes Both Supply Rails Low Noise . . . 19 nV/√Hz Typ at f = 1 kHz Low Input Bias Current . . . 1 pA Typ Fully Specified for Both Single-Supply and Split-Supply Operation Very Low Power . . .
PAGE 2
 SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006 TLV2252 AVAILABLE OPTIONS PACKAGED DEVICES TA VIOmax AT 25°C SMALL OUTLINE† (D) CHIP CARRIER (FK) CERAMIC DIP (JG) PLASTIC DIP (P) TSSOP‡ (PW) CERAMIC FLATPACK (U) −40°C to 125°C 850 µV 1500 µV TLV2252AID TLV2252ID — — — — TLV2252AIP TLV2252IP TLV2252AIPWLE — — — −40°C to 125°C 850 µV 1500 µV TLV2252AQD TLV2252QD — — — — — — — — — — −55°C to 125°C 850
PAGE 3
 SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006 TLV2252I, TLV2252AI TLV2252Q, TLV2252AQ D, P, OR PW PACKAGE (TOP VIEW) 1 8 2 7 3 6 4 5 VDD + 2OUT 2IN − 2IN + TLV2252M, TLV2252AM . . . JG PACKAGE (TOP VIEW) 1OUT 1IN − 1IN + VDD − /GND 1 8 2 7 3 6 4 5 VDD + 2OUT 2IN − 2IN + TLV2252M, TLV2252AM . . .
PAGE 4
IN − IN + Q1 Q5 R4 Q2 R3 Q3 Q4 equivalent schematic (each amplifier) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Q10 R6 Q9 3 Capacitors 6 18 56 76 TLV2254 † Includes both amplifiers and all ESD, bias, and trim circuitry 9 30 Resistors Diodes 38 TLV2252 Transistors R1 Q13 C1 Q12 VDD −/ GND Q11 R5 ACTUAL DEVICE COMPONENT COUNT† Q8 COMPONENT Q7 Q6 VDD + R2 Q15 Q14 D1 Q17 Q16 OUT Template Release Date: 7−11−94 2 2  2
PAGE 5
 SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 V Differential input voltage, VID (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 6
 SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006 TLV2252I electrical characteristics at specified free-air temperature, VDD = 3 V (unless otherwise noted) PARAMETER VIO Input offset voltage αVIO Temperature coefficient of input offset voltage Input offset voltage long-term drift (see Note 4) IIO TA† TEST CONDITIONS TLV2252I MIN 25°C MAX 200 1500 Full range VIC = 0, RS = 50 Ω 0.003 0.003 µV/mo 25°C 0.
PAGE 7
 SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006 TLV2252I electrical characteristics at specified free-air temperature, VDD = 3 V (unless otherwise noted) (continued) PARAMETER TEST CONDITIONS TA† kSVR Supply voltage rejection ratio (∆VDD /∆VIO) VDD = 2.7 V to 8 V, VIC = VDD /2, No load IDD Supply current VO = 1.
PAGE 8
 SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006 TLV2252I electrical characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted) PARAMETER TA† TEST CONDITIONS 25°C VIO Input offset voltage αVIO Temperature coefficient of input offset voltage 25°C 25 C to 85°C Input offset voltage longterm drift (see Note 4) IIO Input offset current TLV2252I MIN VICR VIC = 0, RS = 50 Ω Input bias curr
PAGE 9
 SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006 TLV2252I electrical characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted) (continued) PARAMETER TEST CONDITIONS TA† kSVR Supply voltage rejection ratio (∆VDD /∆VIO) VDD = 4.4 V to 8 V, VIC = VDD /2, No load IDD Supply current VO = 2.
PAGE 10
 SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006 TLV2254I electrical characteristics at specified free-air temperature, VDD = 3 V (unless otherwise noted) PARAMETER VIO Input offset voltage αVIO Temperature coefficient of input offset voltage Input offset voltage long-term drift (see Note 4) IIO TA† TEST CONDITIONS TLV2254I MIN 25°C MAX 200 1500 Full range VIC = 0, RS = 50 Ω VICR 0.003 0.003 µV/mo 25°C 0.
PAGE 11
 SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006 TLV2254I electrical characteristics at specified free-air temperature, VDD = 3 V (unless otherwise noted) (continued) PARAMETER TA† TEST CONDITIONS TLV2254I MIN TYP 95 Supply voltage rejection ratio (∆VDD /∆VIO) VDD = 2.7 V to 8 V, VIC = VDD /2, No load 25°C 80 kSVR Full range 80 IDD Supply current (four amplifiers) VO = 1.
PAGE 12
 SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006 TLV2254I electrical characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted) PARAMETER TA† TEST CONDITIONS MIN 25°C VIO Input offset voltage αVIO Temperature coefficient of input offset voltage 25 C 25°C to 85°C Input offset voltage long-term drift (see Note 4) IIO TLV2254I TYP MAX 200 1500 Full range VDD ± = ± 2.
PAGE 13
 SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006 TLV2254I electrical characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted) (continued) PARAMETER TA† TEST CONDITIONS kSVR Supply voltage rejection ratio (∆VDD /∆VIO) VDD = 4.4 V to 8 V, VIC = VDD /2, No load IDD Supply current (four amplifiers) VO = 2.
PAGE 14
 SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006 TLV2252Q, and TLV2252M electrical characteristics at specified free-air temperature, VDD = 3 V (unless otherwise noted) PARAMETER TA† TEST CONDITIONS TLV2252Q, TLV2252M MIN VIO Input offset voltage αVIO Temperature coefficient of input offset voltage Input offset voltage long-term drift (see Note 4) IIO Input offset current IIB Input bias current 25°C Common-mode
PAGE 15
 SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006 TLV2252Q, and TLV2252M operating characteristics at specified free-air temperature, VDD = 3 V PARAMETER TA† TEST CONDITIONS VO = 0.8 V to 1.4 V, CL = 100 pF‡ RL = 100 kΩ‡, TLV2252Q, TLV2252M MIN TYP 25°C 0.07 0.1 Full range 0.05 TLV2252AQ, TLV2252AM MAX MIN TYP 0.07 0.
PAGE 16
 SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006 TLV2252Q, and TLV2252M electrical characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted) PARAMETER TA† TEST CONDITIONS TLV2252Q, TLV2252M MIN VIO Input offset voltage αVIO Temperature coefficient of input offset voltage Input offset voltage longterm drift (see Note 4) IIO Input offset current IIB Input bias current VICR Common-mode
PAGE 17
 SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006 TLV2252Q, and TLV2252M electrical characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted) (continued) PARAMETER TA† TEST CONDITIONS TLV2252Q, TLV2252M MIN IDD Supply current VO = 2.
PAGE 18
 SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006 TLV2254Q, and TLV2254M electrical characteristics at specified free-air temperature, VDD = 3 V (unless otherwise noted) PARAMETER TA† TEST CONDITIONS TLV2254Q, TLV2254M MIN VIO Input offset voltage αVIO Temperature coefficient of input offset voltage Input offset voltage longterm drift (see Note 4) IIO Input offset current IIB Input bias current VICR Common-mode
PAGE 19
 SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006 TLV2254Q, and TLV2254M electrical characteristics at specified free-air temperature, VDD = 3 V (unless otherwise noted) (continued) PARAMETER TLV2254Q, TLV2254M TA† TEST CONDITIONS MIN IDD Supply current (four amplifiers) VO = 1.
PAGE 20
 SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006 TLV2254Q, and TLV2254M electrical characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted) PARAMETER TA† TEST CONDITIONS TLV2254Q, TLV2254M MIN VIO Input offset voltage αVIO Temperature coefficient of input offset voltage Input offset voltage long-term drift (see Note 4) IIO Input offset current IIB Input bias current VICR Common-mode
PAGE 21
 SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006 TLV2254Q, and TLV2254M electrical characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted) (continued) PARAMETER TEST CONDITIONS TLV2254Q, TLV2254M TA† MIN Supply current (four amplifiers) IDD 25°C VO = 2.
PAGE 22
 SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006 TYPICAL CHARACTERISTICS Table of Graphs FIGURE VIO Input offset voltage Distribution vs Common-mode voltage 2−5 6, 7 αVIO IIB /IIO Input offset voltage temperature coefficient Distribution 8 − 11 Input bias and input offset currents vs Free-air temperature 12 VI Input voltage vs Supply voltage vs Free-air temperature 13 14 VOH VOL High-level output voltage vs
PAGE 23
 SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006 TYPICAL CHARACTERISTICS DISTRIBUTION OF TLV2252 INPUT OFFSET VOLTAGE DISTRIBUTION OF TLV2252 INPUT OFFSET VOLTAGE 20 20 1020 Amplifiers From 1 Wafer Lot VDD = ± 2.5 V TA = 25°C Precentage of Amplifiers − % Precentage of Amplifiers − % 1020 Amplifiers From 1 Wafer Lot VDD = ± 1.5 V TA = 25°C 15 10 5 0 −1.6 −0.8 0 0.8 VIO − Input Offset Voltage − mV 15 10 5 0 −1.
PAGE 24
 SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006 TYPICAL CHARACTERISTICS INPUT OFFSET VOLTAGE† vs COMMON-MODE INPUT VOLTAGE INPUT OFFSET VOLTAGE† vs COMMON-MODE INPUT VOLTAGE 1 1 VDD = 3 V RS = 50 Ω TA = 25°C 0.8 VIO − Input Offset Voltage − mV 0.6 VIO − Input Offset Voltage − mV VDD = 5 V RS = 50 Ω TA = 25°C 0.8 0.4 0.2 0 −0.2 0.6 0.4 0.2 0 −0.2 ÁÁ ÁÁ −0.4 ÁÁ ÁÁ −0.6 −0.4 −0.6 −0.8 −0.
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 SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006 TYPICAL CHARACTERISTICS DISTRIBUTION OF TLV2254 INPUT OFFSET VOLTAGE TEMPERATURE COEFFICIENT 25 62 Amplifiers From 1 Wafer Lot VDD± = ± 1.5 V P Package TA = 25°C to 85°C 20 62 Amplifiers From 1 Wafer Lot VDD ± = ± 2.
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 SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006 TYPICAL CHARACTERISTICS INPUT VOLTAGE†‡ vs FREE-AIR TEMPERATURE HIGH-LEVEL OUTPUT VOLTAGE†‡ vs HIGH-LEVEL OUTPUT CURRENT 5 3 VDD = 5 V VDD = 3 V ÁÁ VOH − High-Level Output Voltage − V VI − Input Voltage − V 4 3 | VIO | ≤ 5 mV 2 1 0 −1 −55 −35 −15 5 25 45 65 85 105 TA − Free-Air Temperature − °C 125 ÁÁ ÁÁ ÁÁ 2.5 TA = − 40°C 2 TA = 25°C 1.
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 SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006 TYPICAL CHARACTERISTICS HIGH-LEVEL OUTPUT VOLTAGE†‡ vs HIGH-LEVEL OUTPUT CURRENT LOW-LEVEL OUTPUT VOLTAGE†‡ vs LOW-LEVEL OUTPUT CURRENT 5 1.4 VDD = 5 V VIC = 2.5 V ÁÁ ÁÁ 1.2 4 VOL − Low-Level Output Voltage − V VOH − High-Level Output Voltage − V VDD = 5 V TA = − 40°C 3 TA = 25°C 2 TA = 85°C ÁÁ ÁÁ 1 TA = 125°C 0 0 200 400 600 TA = 125°C 1 TA = 85°C 0.
PAGE 28
 SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006 TYPICAL CHARACTERISTICS DIFFERENTIAL INPUT VOLTAGE‡ vs OUTPUT VOLTAGE SHORT-CIRCUIT OUTPUT CURRENT † vs FREE-AIR TEMPERATURE 1000 VO = 2.5 V VDD = ± 5 V 10 9 8 VID = − 100 mV 7 6 5 4 3 2 1 600 400 200 0 −200 −400 −600 −800 VID = 100 mV 0 −1 −75 −50 −25 0 25 50 75 100 TA − Free-Air Temperature − °C VDD = 3 V RI = 50 kΩ VIC = 1.
PAGE 29
 SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006 TYPICAL CHARACTERISTICS LARGE-SIGNAL DIFFERENTIAL VOLTAGE† AMPLIFICATION AND PHASE MARGIN vs FREQUENCY AVD A VD − Large-Signal Differential Voltage Amplification − dB 60 ÁÁ ÁÁ ÁÁ 180° VDD = 5 V RL = 50 kΩ CL= 100 pF TA = 25°C 135° 40 90° Phase Margin 20 45° Gain 0 0° −20 φom m − Phase Margin 80 −45° −40 10 3 10 4 10 5 10 6 f − Frequency − Hz −90° 10 7 Fig
PAGE 30
 SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006 TYPICAL CHARACTERISTICS LARGE-SIGNAL DIFFERENTIAL†‡ VOLTAGE AMPLIFICATION vs FREE-AIR TEMPERATURE LARGE-SIGNAL DIFFERENTIAL†‡ VOLTAGE AMPLIFICATION vs FREE-AIR TEMPERATURE 10 4 VDD = 3 V VIC = 1.5 V VO = 0.5 V to 2.
PAGE 31
 SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006 TYPICAL CHARACTERISTICS COMMON-MODE REJECTION RATIO†‡ vs FREE-AIR TEMPERATURE COMMON-MODE REJECTION RATIO† vs FREQUENCY 94 VDD = 5 V VIC = 2.5 V CMMR − Common-Mode Rejection Ratio − dB CMRR − Common-Mode Rejection Ratio − dB 100 TA = 25°C 80 VDD = 3 V VIC = 1.
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 SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006 TYPICAL CHARACTERISTICS TLV2252 SUPPLY CURRENT † vs SUPPLY VOLTAGE SUPPLY-VOLTAGE REJECTION RATIO† vs FREE-AIR TEMPERATURE Á Á 120 VDD = 2.
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 SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006 TYPICAL CHARACTERISTICS SLEW RATE†‡ vs FREE-AIR TEMPERATURE INVERTING LARGE-SIGNAL PULSE RESPONSE† 0.2 0.16 VDD = 3 V RL = 50 kΩ CL = 100 pF AV = −1 TA = 25°C 2.5 SR − VO − Output Voltage − V SR − Slew Rate − V/ µ s 3 VDD = 5 V RL = 50 kΩ CL = 100 pF AV = 1 0.12 SR + 0.08 0.04 2 1.5 1 0.
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 SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006 TYPICAL CHARACTERISTICS INVERTING SMALL-SIGNAL PULSE RESPONSE† VOLTAGE-FOLLOWER LARGE-SIGNAL PULSE RESPONSE† 0.95 5 VDD = 5 V RL = 50 kΩ CL = 100 pF AV = 1 TA = 25°C 0.9 VO − Output Voltage − V VO − Output Voltage − V 4 VDD = 3 V RL = 50 kΩ CL = 100 pF AV = − 1 TA = 25°C 3 2 0.85 0.8 0.75 0.7 1 0.65 0.
PAGE 35
 SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006 TYPICAL CHARACTERISTICS EQUIVALENT INPUT NOISE VOLTAGE† vs FREQUENCY VOLTAGE-FOLLOWER SMALL-SIGNAL PULSE RESPONSE† 60 2.65 VO VO − Output Voltage − V 2.6 V n − Equivalent Input Noise Voltage − nV/ Hz VDD = 5 V RL = 50 kΩ CL = 100 pF AV = 1 TA = 25°C 2.55 2.5 2.45 2.
PAGE 36
 SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006 TYPICAL CHARACTERISTICS INTEGRATED NOISE VOLTAGE† vs FREQUENCY THD + N − Total Harmonic Distortion Plus Noise − % TOTAL HARMONIC DISTORTION PLUS NOISE† vs FREQUENCY Integrated Noise Voltage − µ V 100 Calculated Using Ideal Pass-Band Filter Low Frequency = 1 Hz TA = 25°C 10 1 0.1 101 1 10 2 10 3 f − Frequency − Hz 10 4 10 5 1 AV = 100 0.1 AV = 10 0.
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 SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006 TYPICAL CHARACTERISTICS PHASE MARGIN vs LOAD CAPACITANCE 75° GAIN MARGIN vs LOAD CAPACITANCE 20 Rnull = 200 Ω TA = 25°C Rnull = 500 Ω Rnull = 500 Ω 60° Gain Margin − dB φom m − Phase Margin 15 45° Rnull = 100 Ω Rnull = 50 Ω 30° Rnull = 10 Ω 50 kΩ VI 0° 101 Rnull = 100 Ω 10 Rnull = 50 Ω Rnull = 10 Ω 50 kΩ 15° Rnull = 200 Ω 5 VDD + Rnull − + Rnull = 0 Rn
PAGE 38
 SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006 APPLICATION INFORMATION driving large capacitive loads The TLV2252 is designed to drive larger capacitive loads than most CMOS operational amplifiers. Figure 56 and Figure 57 illustrate its ability to drive loads up to 1000 pF while maintaining good gain and phase margins (Rnull = 0).
PAGE 39
 SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006 APPLICATION INFORMATION macromodel information Macromodel information provided was derived using Microsim Parts, the model generation software used with Microsim PSpice. The Boyle macromodel (see Note 5) and subcircuit in Figure 61 are generated using the TLV2252 typical electrical and operating characteristics at TA = 25°C.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 25-Sep-2013 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
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PACKAGE MATERIALS INFORMATION www.ti.com 12-Aug-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TLV2252AIDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLV2252AIPWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1 TLV2252IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 12-Aug-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLV2252AIDR SOIC D 8 2500 340.5 338.1 20.6 TLV2252AIPWR TSSOP PW 8 2000 367.0 367.0 35.0 TLV2252IDR SOIC D 8 2500 340.5 338.1 20.6 TLV2254AIDR SOIC D 14 2500 367.0 367.0 38.0 TLV2254AIPWR TSSOP PW 14 2000 367.0 367.0 35.0 TLV2254IDR SOIC D 14 2500 367.0 367.0 38.
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MECHANICAL DATA MCER001A – JANUARY 1995 – REVISED JANUARY 1997 JG (R-GDIP-T8) CERAMIC DUAL-IN-LINE 0.400 (10,16) 0.355 (9,00) 8 5 0.280 (7,11) 0.245 (6,22) 1 0.063 (1,60) 0.015 (0,38) 4 0.065 (1,65) 0.045 (1,14) 0.310 (7,87) 0.290 (7,37) 0.020 (0,51) MIN 0.200 (5,08) MAX Seating Plane 0.130 (3,30) MIN 0.023 (0,58) 0.015 (0,38) 0°–15° 0.100 (2,54) 0.014 (0,36) 0.008 (0,20) 4040107/C 08/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters).
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.