Datasheet

C
L
5 pF
C
L
5 pF
50 Ω
50 Ω
t
r
t
f
CLOCK
80%
50%
20%
t
r
t
f
2 V
0.8 V
DATA
1.4 V
TLK1211RCP
www.ti.com SLLS658D – SEPTEMBER 2006– REVISED APRIL 2011
Figure 8. Transmitter Test Setup
LVTTL OUTPUT SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
r(RBC)
Clock rise time 0.3 1.5
ns
t
f(RBC)
Clock fall time 0.3 1.5
80% to 20% output voltage, C = 5 pF (see
Figure 9)
t
r
Data rise time 0.3 1.5
ns
t
f
Data fall time 0.3 1.5
Data setup time (RD0–RD9), Data
t
su(D1)
TBI normal mode, (see Figure 3) 2.5 ns
valid prior to RBC0 rising
Data hold time (RD0–RD9), Data valid
t
h(D1)
TBI normal mode, (see Figure 3) 2 ns
after RBC0 rising
t
su(D2)
Data setup time (RD0–RD4) DDR mode, R
ω
= 125 MHz, (see Figure 4) 2 ns
t
h(D2)
Data hold time (RD0–RD4) DDR mode, R
ω
= 125 MHz, (see Figure 4) 0.8 ns
t
su(D3)
Data setup time (RD0–RD9) TBI half-rate mode, R
ω
= 125 MHz, (see Figure 2) 2.5 ns
t
h(D3)
Data hold time (RD0–RD9) TBI half-rate mode, R
ω
= 125 MHz, (see Figure 2) 1.5 ns
Figure 9. TTL Data I/O Valid Levels for AC Measurement
TRANSMITTER TIMING REQUIREMENTS
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
su(D4)
Data setup time (TD0–TD9) 1.6
TBI modes ns
t
h(D4)
Data hold time (TD0–TD9) 0.8
t
su(D5)
Data setup time (TD0–TD9) 0.7
DDR modes ns
t
h(D5)
Data hold time (TD0–TD9) 0.5
t
r
, t
f
TD[0,9] data rise and fall time See Figure 9 2 ns
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