Datasheet

TLE208x, TLE208xA, TLE208xY
EXCALIBUR HIGH-SPEED JFET-INPUT
OPERATIONAL AMPLIFIERS
SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLE2081Y chip information
This chip, when properly assembled, displays characteristics similar to the TLE2081. Thermal compression or
ultrasonic bonding may be used on the doped-aluminum bonding pads. Chips may be mounted with conductive
epoxy or a gold-silicon preform.
BONDING PAD ASSIGNMENTS
CHIP THICKNESS: 15 TYPICAL
BONDING PADS: 4 × 4 MINIMUM
T
J
max = 150°C
TOLERANCES ARE ±10%.
ALL DIMENSIONS ARE IN MILS.
PIN (4) IS INTERNALLY CONNECTED
TO BACKSIDE OF THE CHIP.
+
–
OUT
IN+
IN–
V
CC+
(6)
(3)
(2)
(5)
(1)
(7)
(4)
OFFSET N1
OFFSET N2
V
CC–
58
85
(1)
(2)
(4) (5)
(6)
(7)
(8)
(3)