Datasheet
µ
SLOS193B − FEBRUARY 1997 − REVISED MAY 2004
58
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
macromodel information
Macromodel information provided was derived using Microsim Parts, the model generation software used
with Microsim PSpice. The Boyle macromodel (see Note 5) and the subcircuit in Figure 46 were generated
using the TLE206x typical electrical and operating characteristics at 25°C. Using this information, output
simulations of the following key parameters can be generated to a tolerance of 20% (in most cases).
D Unity-gain frequency
D Common-mode rejection ratio
D Phase margin
D DC output resistance
D AC output resistance
D Short-circuit output current limit
D Maximum positive output voltage swing
D Maximum negative output voltage swing
D Slew rate
D Quiescent power dissipation
D Input bias current
D Open-loop voltage amplification
NOTE 5: G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, “Macromodeling of Integrated Circuit Operational Amplifiers”, IEEE Journal
of Solid-State Circuits, SC-9, 353 (1974).
OUT
+
−
+
−
+
−
+
−
+
−
+
−
+
−
+−
.subckt TLE2062 1 2 3 4 5
c1 11 12 1.457E−12
c2 6 7 15.00E−12
dc 5 53 dx
de 54 5 dx
dlp 90 91 dx
dln 92 90 dx
dp 4 3 dx
egnd 99 0 poly (2) (3,0) (4,0) 0 .5 .5
fb 7 99 poly (5) vb vc ve vlp
+ vln 0 4.357E6 − 4E6 4E6 4E6 − 4E6
ga 6 0 11 12 188.5E−6
gcm 0 6 10 99 3.352E−9
iss 3 10 dc 51.00E−6
hlim 90 0 vlim 1k
j1 11 2 10 jx
j2 12 1 10 jx
r2 6 9 100.0E3
V
CC+
rp
IN−
2
IN+
1
V
CC−
rd1
11
j1 j2
10
rss iss
3
12
rd2
ve
54
de
dp
vc
dc
4
C1
53
r2
6
9
egnd
vb
fb
C2
gcm
ga
vlim
8
5
ro1
ro2
hlim
90
dip
91
din
92
vinvip
99
7
rd1 4 11 5.305E3
rd2 4 12 5.305E3
r01 8 5 280
r02 7 99 280
rp 3 4 113.2E3
rss 10 99 3.922E6
vb 9 0 dc 0
vc 3 53 dc 2
ve 54 4 dc 2
vlim 7 8 dc 0
vlp 91 0 dc 50
vln 0 92 dc 50
.model dx D(Is=800.0E−18)
.model jx PJF(Is=2.000E−12 Beta = 423E−6
+ Vto = − 1)
.ends
Figure 46. Boyle Macromodel and Subcircuit
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