Datasheet

TLC542C, TLC542I
8-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 INPUTS
SLAS075C – FEBRUARY 1989 – REVISED JUNE 2001
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions, V
CC
= 4.75 to 5.5 V
MIN NOM MAX UNIT
Supply voltage, V
CC
4.75 5 5.5 V
Positive reference voltage, V
ref+
(see Note 2) V
ref–
V
CC
V
CC
+ 0.1 V
Negative reference voltage, V
ref–
(see Note 2) –0.1 0 V
ref+
V
Differential reference voltage, V
ref+
– V
ref–
(see Note 2) 1 V
CC
V
CC
+ 0.2 V
Analog input voltage (see Note 3) 0 V
CC
V
High-level control input voltage, V
IH
2 V
Low-level control input voltage, V
IL
0.8 V
Setup time, address bits at data input before I/O CLOCK↑, t
su(A)
400 ns
Hold time, address bits after I/O CLOCK↑, t
h(A)
0 ns
Hold time, CS low after 8th I/O CLOCK↑, t
h(CS)
0 ns
Setup time, CS low before clocking in first address bit, t
su(CS)
(see Note 4) 3.8 µs
Input/output clock frequency, f
(clock I/O)
0 1.1 MHz
Input/output clock high, t
w(H I/O)
404 ns
Input/output clock low, t
w(L I/O)
404 ns
I/O CLOCK transition time t
t
(see Note 3)
f
clock(I/O)
≤ 525 kHz 100
ns
I/O
CLOCK
transition
time
,
t
t
(see
Note
3)
f
clock(I/O)
> 525 kHz 40
ns
O
p
erating free air tem
p
erature T
A
TLC542C 0 70
°C
Operating
free
-
air
temperature
,
T
A
TLC542I –40 85
°C
NOTES: 2. Analog input voltages greater than that applied to REF+ convert as all ones (11111111), while input voltages less than that applied
to REF– convert as all zeros (00000000). For proper operation, REF+ must be at least 1 V higher than REF–. Also, the total
unadjusted error may increase as this differential reference voltage falls below 4.75 V.
3. This is the time required for the clock input signal to fall from V
IH
min to V
IL
max or to rise from V
IL
max to V
IH
min. In the vicinity
of normal room temperature, the devices function with input clock transition time as slow as 2 µs for remote data acquisition
applications where the sensor and the A/D converter are placed several feet away from the controlling microprocessor.
4. To minimize errors caused by noise at the chip select input, the internal circuitry waits for two rising edges and one falling edge of
the internal system clock after CS
↓ before responding to control input signals. The CS setup time is given by the t
su(CS)
specifications. Therefore, no attempt should be made to clock-in address data until the minimum chip select setup time has elapsed.
electrical characteristics over recommended operating temperature range, V
CC
= V
ref+
= 4.75 V to
5.5 V, f
(clock I/O)
= 1.1 MHz (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
†
MAX UNIT
V
OH
High-level output voltage (DATA OUT) V
CC
= 4.75 V, I
OH
= –360 µA 2.4 V
V
OL
Low-level output voltage V
CC
= 4.75 V, I
OL
= 1.6 mA 0.4 V
Off state (high im
p
edance state) out
p
ut current
V
O
= V
CC
, CS at V
CC
10
µA
Off
-
state
(high
-
impedance
state)
output
current
V
O
= 0, CS at V
CC
–10
µ
A
I
IH
High-level input current V
I
= V
CC
0.005 2 µA
I
IL
Low-level input current V
I
= 0 –0.005 –2.5 µA
I
CC
Operating supply current CS at 0 V 1.2 2 mA
Selected channel leakage current
Selected channel at V
CC
and
unselected channel at 0 V
0.4
µA
Selected
channel
leakage
current
Selected channel at 0 V and
unselected channel at V
CC
–0.4
µ
A
I
ref
Maximum static analog reference current into REF+ V
ref+
= V
CC
, V
ref–
= GND 10 µA
C
i
In
p
ut ca
p
acitance
Analog inputs 7 55
p
F
C
i
Input
capacitance
Control inputs 5 15
pF
†
All typical values are at T
A
= 25°C.