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 

SLAS293 − DECEMBER 2001

    

     

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FEATURES

200-KSPS Sampling Rate

D Built-In Conversion Clock

D INL: ±2.5 LSB Max,

DNL: 2 to −1 LSB Max

D SINAD = 84.5 dB, SFDR = 95 dB,

THD = 94 dB at 15 kHz f

, 200 KSPS

D SPI/DSP-Compatible Serial Interfaces With

SCLK Input up to 15 MHz

D Single 5-V Supply

D Rail-to-Rail Analog Input With 500 kHz BW

D Two Input Options Available:

− TLC4541 − Single Channel Input

− TLC4545 − Single Channel,

Pseudo-differential Input

D (TLC4541) Optimized DSP Interface −

Requires FS Input Only

D Low Power With Auto-Power Down

− Operating Current: 3.5 mA

− Auto-Power Down Current: 5 µA

D Pin Compatible 12/14/16-Bit Family in 8-Pin

SOIC and MSOP Packages

APPLICATIONS

ATE System

D Industrial Process Control

D Measurement

D Motor Control

DESCRIPTION

The TLC4541 and TLC4545 are a family of high

performance, 16-bit, low power, miniature CMOS

analog-to-digital converters (ADCs). These devices

operate from a single 5-V supply. Devices are available

with single, dual, or single pseudo-differential inputs. All

of these devices have a chip select (CS

), serial clock

(SCLK), and serial data output (SDO) that provides a

direct 3-wire interface to the serial port of most popular

host microprocessors (SPI interface). When interfaced

with a DSP, a frame sync signal (FS) is used to indicate

the start of a serial data frame on either pin 1 (CS

) or pin

7 (FS) for the TLC4541. The TLC4545 ADC connects

to the DSP via pin 1 only (CS

The TLC4541 and TLC4545 are designed to operate

with low power consumption. The power saving feature

is further enhanced with an auto-power down mode.

This product family features a high-speed serial link to

modern host processors with an external SCLK up to

15 MHz. Both families use a built-in oscillator as the

conversion clock, providing a 2.94 µs maximum

conversion time.

SDO

SCLK

REF

GND

AIN

TLC4541

D OR DGK Package

(TOP VIEW)

SDO

SCLK

AIN(−)

REF

GND

AIN(+)

TLC4545

D OR DGK Package

(TOP VIEW)

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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Summary of content (27 pages)

PAGE 1
SLAS293 − DECEMBER 2001 FEATURES D 200-KSPS Sampling Rate D Built-In Conversion Clock D INL: ±2.5 LSB Max, D D D D D D D D DNL: 2 to −1 LSB Max SINAD = 84.
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SLAS293 − DECEMBER 2001 AVAILABLE OPTIONS PACKAGED DEVICES TA −40°C to 85°C 8-MSOP (DGK) 8-SOIC (D) TLC4541IDGK (PKG Code = ALM) TLC4541ID TLC4545IDGK (PKG Code = AME) TLC4545ID functional block diagram TLC4541 TLC4545 VDD VDD REF AIN REF S/H OSC SCLK CS FS LOW POWER SAR ADC AIN (+) SDO AIN (−) Conversion Clock OSC CONTROL LOGIC SCLK CS LOW POWER SAR ADC Conversion Clock CONTROL LOGIC GND GND 2 S/H www.ti.
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SLAS293 − DECEMBER 2001 Terminal Functions TLC4541 single channel unipolar ADCs TERMINAL NAME NO. I/O DESCRIPTION AIN 4 I Analog input channel CS 1 I Chip select. A high-to-low transition on the CS input removes SDO from a high-impedance state within a maximum delay time. If the TLC4541 is attached to a dedicated TMS320 DSP serial port using the FS input, CS can be grounded. FS 7 I DSP frame sync input. Indication of a start of a serial data frame.
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SLAS293 − DECEMBER 2001 absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Supply voltage, GND to VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 6.5V Analog input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to VDD+0.3 V Reference input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . .
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SLAS293 − DECEMBER 2001 electrical characteristics over recommended operating free-air temperature range, VDD = 5 V, VREF = 4.
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SLAS293 − DECEMBER 2001 timing requirements, VDD = 5 V, VREF = 4.096 V, SCLK frequency = 15 MHz (unless otherwise specified) MIN TYP MAX UNIT tcyc(SCLK) tw1 SCLK cycle time, VDD = 4.5 V to 5.
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SLAS293 − DECEMBER 2001 TYPICAL CHARACTERISTICS DNL − Differential Nonlinearity − LSB DIFFERENTIAL NONLINEARITY 2.5 1.5 0.5 −0.5 −1.5 −2.5 0 10000 20000 30000 40000 50000 60000 Code Figure 1 INL − Integral Nonlinearity − LSB INTEGRAL NONLINEARITY 2.5 2 1.5 1 0.5 0 −0.5 −1 −1.5 −2 −2.5 0 10000 20000 30000 40000 50000 60000 Code Figure 2 www.ti.
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SLAS293 − DECEMBER 2001 TYPICAL CHARACTERISTICS FFT 0 FFT = 15 kHz, VDD = VREF = 5 V, 200 KSPS Magnitude − dB −20 −40 −60 −80 −100 −120 −140 −160 0 10 20 30 40 50 60 70 80 90 100 fi − Input Frequency − kHz Figure 3 FFT 0 FFT = 1.5 kHz, VDD = VREF = 5 V, 200 KSPS Magnitude − dB −20 −40 −60 −80 −100 −120 −140 −160 0 10 20 30 40 50 60 fi − Input Frequency − kHz Figure 4 8 www.ti.
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SLAS293 − DECEMBER 2001 TYPICAL CHARACTERISTICS SIGNAL-TO NOISE RATIO vs INPUT FREQUENCY TOTAL HARMONIC DISTORTION vs INPUT FREQUENCY 88 −80 THD − Total Harmonic Distortion − dB VDD = VREF = 5 V SNR − Signal-To-Noise Ration − dB 86 84 82 80 78 76 74 72 70 VDD = VREF = 5 V −82 −84 −86 −88 −90 −92 −94 −96 −98 0 20 40 60 80 100 fi − Input Frequency − kHz −100 120 0 20 Figure 5 −84 85.
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SLAS293 − DECEMBER 2001 TYPICAL CHARACTERISTICS TOTAL HARMONIC DISTORTION vs REFERENCE VOLTAGE SIGNAL-TO-NOISE RATIO vs REFERENCE VOLTAGE 86.6 −97.5 fi = 1.5 kHz, 200 KSPS −98.0 SNR − Signal-To-Noise Ration − dB THD − Total Harmonic Distortion − dB 86.4 −98.5 −99.0 −99.5 −100.0 −100.5 86.2 86.0 85.8 85.6 85.4 85.2 85.0 84.8 −101.0 4.0 4.5 84.6 4.0 5.0 VREF − Reference Voltage − V Figure 9 MINIMUM DIFFERENTIAL NONLINEARITY vs REFERENCE VOLTAGE 2.
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SLAS293 − DECEMBER 2001 TYPICAL CHARACTERISTICS INTEGRAL NONLINEARITY vs REFERENCE VOLTAGE 2.0 Integral Nonlinearity − LSB 1.5 1.0 0.5 0.0 −0.5 −1.0 4.0 4.5 5.0 VREF − Reference Voltage − V Figure 13 www.ti.
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SLAS293 − DECEMBER 2001 PRINCIPLES OF OPERATION control and timing device initialization/RESET cycle The TLC4541/45 each require one RESET cycle after power-on for initialization in order to operate properly. This RESET cycle is initiated by asserting the CS pin (pin 1) low for a minimum duration of at least one SCLK falling edge but no more than 8 SCLK falling edges in length. The RESET cycle is terminated by asserting CS high.
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SLAS293 − DECEMBER 2001 PRINCIPLES OF OPERATION control and timing (continued) sampling and conversion cycle TLC4541: Control via pin 1, CS (FS = 1 at the falling edge of CS)− The falling edge of CS is the start of the cycle. Transitions on CS can occur when SCLK is high or low. The MSB may be read on the first falling SCLK edge after CS is low. Output data changes on the rising edge of SCLK.
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SLAS293 − DECEMBER 2001 PRINCIPLES OF OPERATION control via pin 1 (CS, DSP interface) All devices are compatible with this mode of operation. The FS signal from a DSP is connected directly to the CS input of the ADC. A falling edge on the CS input while SCLK is high or low initiates the cycle. (For TLC4541 in this configuration, the FS input is tied to VDD.) Enough time should be allowed before the next rising CS edge so that the conversion cycle is not terminated prematurely.
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SLAS293 − DECEMBER 2001 PRINCIPLES OF OPERATION tcyc tcyc(SCLK) 1 SCLK tconv ts 5 2 14 16 15 1 17, 24 tw1 tsu1 t(PWRDWN) th2 tw2 CS tw3 th1 td2 SDO td3 LSB+2 MSB MSB LSB LSB+1 td1 Figure 18. Critical Timing: Control Via CS Input (FS = 1 for TLC4541) tconv ts 2 1 SCLK 5 t(PWRDWN) th2 th4 1 17, 24 16 15 14 tsu5 tsu4 CS tw4 t(PWRDWN) td2 FS ÎÎ ÎÎ tsu3 SDO ÎÎÎ ÎÎÎ td3 LSB+2 MSB LSB+1 LSB td4 MSB Figure 19.
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SLAS293 − DECEMBER 2001 PRINCIPLES OF OPERATION 2 1 SCLK 8 th7 9 2 1 tsu7 th7 8 9 2 1 tsu6 tcyc(reset) CS tcyc(reset) OR Normal Cycle Begins FS ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ Initialization Cycle (Reset) SDO MSB MSB Figure 21. Critical Timing: Initialization Cycle (TLC4541 Only) ÎÎ ÎÎ MSB MSB−1 detailed description The TLC4541/5 are successive approximation (SAR) ADCs utilizing a charge-redistribution DAC. Figure 22 shows a simplified version of the ADC.
PAGE 17
SLAS293 − DECEMBER 2001 PRINCIPLES OF OPERATION pseudo-differential inputs The TLC4545 operate in pseudo-differential mode. The inverted input is available on pin 5. The inverted input can tolerate a maximum input ripple of ±0.2 V. It is normally used for zero-scale offset cancellation or ground noise rejection. serial interface Output data format is binary (unipolar straight binary).
PAGE 18
SLAS293 − DECEMBER 2001 APPLICATION INFORMATION 5V DSP to Single TLC4541 0.1 µF REF 0.1 µF 10 kΩ 10 kΩ VDD FS FSX0 SD0 DR0 DSP CLKX0 SCLK CLKR0 CS TLC4541 REF AIN GND 5V DSP to Single TLC4545 0.1 µF REF 0.1 µF 10 kΩ 10 kΩ CS/FS FSX0 SD0 DR0 DSP SCLK CLKX0 CLKR0 VDD REF TLC4545 AIN(+) AIN(−) GND DSP to Multiple TLC4541s XF0 FSX0 DR0 DSP CLKX0 CLKR0 XF1 Ext Ref Input 5V REF 0.1 µF 5V 0.1 µF 0.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
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PACKAGE MATERIALS INFORMATION www.ti.com 16-Aug-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TLC4541IDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 TLC4545IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 16-Aug-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLC4541IDGKR VSSOP DGK 8 2500 367.0 367.0 35.0 TLC4545IDR SOIC D 8 2500 367.0 367.0 35.
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