Datasheet

TLC3544, TLC3548
5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL
ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS
SLAS266C – OCTOBER 2000 – REVISED MAY 2003
28
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
conversion operation (continued)
CS
FS
SDI
INT
SDO
*** Command = Configure Write for Mode 11, FIFO
Threshold = 1/2 Full, Sweep Sequence: 0–0–2–2
** COMMAND = Select Any Channel
* COMMAND = Read FIFO
*
Configure
Conversion
From CH0
Conversion
From CH2
Conversion
From CH2
Conversion
From CH0
1st SWEEP
1st FIFO Read
REPEAT
2nd FIFO Read
CH0 CH0 CH2 CH2 CH0
Read FIFO After 1st SWEEP Completed
CSTART
*** ** ****** *
Possible Signal
Don’t Care
Figure 20. Mode 11, CSTART Triggers Samplings/Conversions
conversion clock and conversion speed
The conversion clock source can be the internal OSC, or the external clock SCLK. When the external clock is
used, the conversion clock is equal to SCLK/4. It takes 18 conversion clocks plus 15 ns to finish the conversion.
If the external clock is selected, the conversion time (not including sampling time) is 18X(4/f
SCLK
)+15 ns. Table 4
shows the maximum conversion rate (including sampling time) when the analog input source resistor is 1 kΩ.
Table 4. Maximum Conversion Rate
DEVICE SAMPLING MODE CONVERSION CLK
MAX SCLK
(MHz)
CONVERSION
TIME (us)
RATE
(KSPS)
Short (16 SCLK) External SCLK/4 10 8.815 113.4
TLC3544/48
Long (48 SCLK) External SCLK/4 25 4.815 207.7
TLC3544/48
(Rs = 1000)
Short (16 SCLK) Internal 6.5 MHz 10 4.385 228
()
Long (48 SCLK) Internal 6.5 MHz 25 4.705 212.5
FIFO operation
76543210ADC
×8
FIFO
SOD
Serial
FIFO Full
FIFO 3/4 Full
FIFO 1/2 Full
FIFO 1/4 Full
FIFO Threshold Pointer
Figure 21. FIFO Structure