Datasheet

Q3 Q6 Q9 Q12 Q14 Q16
Q2 Q5 Q7 Q8 Q10 Q11
D1
Q17Q15Q13
Q4Q1
R5
C1
V
DD +
IN +
IN −
R3 R4 R1 R2
OUT
V
DD−
TLC2272-Q1 , TLC2272A-Q1
TLC2274-Q1, TLC2274A-Q1
SGLS007E –FEBRUARY 2003–REVISED JANUARY 2012 www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
AVAILABLE OPTIONS
PACKAGED DEVICES
(1)(2)
T
A
V
IO
max At 25°C
SMALL OUTLINE (D) TSSOP (PW)
950 μV TLC2272AQDRQ1 TLC2272AQPWRQ1
-40°C to 125°C
2.5 mV TLC2272QDRQ1 TLC2272QPWRQ1
950 μV TLC2274AQDRQ1 TLC2274AQPWRQ1
-40°C to 125°C
2.5 mV TLC2274QDRQ1 TLC2274QPWRQ1
(1) For the most current package and ordering information, see the Package Option Addendum at the end
of this document, or see the TI web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
Equivalent Schematic (Each Amplifier)
2 Submit Documentation Feedback Copyright © 2003–2012, Texas Instruments Incorporated
Product Folder Link(s): TLC2272-Q1 TLC2272A-Q1 TLC2274-Q1 TLC2274A-Q1