Datasheet

TL16C752B

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SLLS405C –DECEMBER 1999–REVISED JUNE 2010

PRINCIPLES OF OPERATION

Each register is selected using address lines A[0], A[1], A[2] and, in some cases, bits from other registers. The

programming combinations for register selection are shown in Table 7. All registers shown in bold are accessed

by a combination of address pins and register bits.

Table 7. Register Map – Read/Write Properties

(1)

A[2] A[1] A[0] READ MODE WRITE MODE

0 0 0 Receive holding register (RHR) Transmit holding register (THR)

0 0 1 Interrupt enable register (IER) Interrupt enable register

0 1 0 Interrupt identification register (IIR) FIFO control register (FCR)

0 1 1 Line control register (LCR) Line control register

1 0 0 Modem control register (MCR) Modem control register

1 0 1 Line status register (LSR)

1 1 0 Modem status register (MSR)

1 1 1 Scratch register (SPR) Scratch register (SPR)

0 0 0 Divisor latch LSB (DLL) Divisor latch LSB (DLL)

0 0 1 Divisor latch MSB (DLH) Divisor latch MSB (DLH)

0 1 0 Enhanced feature register (EFR) Enhanced feature register

1 0 0 Xon-1 word Xon-1 word

1 0 1 Xon-2 word Xon-2 word

1 1 0 Xoff-1 word Xoff-1 word

1 1 1 Xoff-2 word Xoff-2 word

1 1 0 Transmission control register (TCR) Transmission control register

1 1 1 Trigger level register (TLR) Trigger level register

1 1 1 FIFO ready register

(1) DLL and DLH are accessible only when LCR bit-7, is 1.

Enhanced feature register, Xon1, 2 and Xoff1, 2 are accessible only when LCR is set to 10111111 (8hBF).

Transmission control register and trigger level register are accessible only when EFR[4] = 1 and MCR[6] = 1, i.e.. EFR[4] and MCR[6]

are read/write enables.

FIFORdy register is accessible only when CSA and CSB = 0, MCR [2] = 1 and loopback is disabled (MCR[4]=0).

MCR[7] can only be modified when EFR[4] is set.

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