Datasheet

TL16C554A, TL16C554AI
ASYNCHRONOUS-COMMUNICATIONS ELEMENT
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SLLS509E − AUGUST 2001 − REVISED JUNE 2010
36
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
scratchpad register
The scratchpad register is an 8-bit read/write register that has no effect on any ACE channel. It is intended to
be used by the programmer to hold data temporarily.
TXRDY operation
In mode 0, TXRDY is asserted (low) when the transmit FIFO is empty; it is released (high) when the FIFO
contains at least one byte. In this way, the FIFO is written with 16 bytes when TXRDY
is asserted (low).
In mode 1, TXRDY
is asserted (low) when the transmit FIFO is not full; in this mode, the transmit FIFO is written
with another byte when TXRDY
is asserted (low).
Driver
Optional
Driver
External
Clock
Optional
Clock
Output
Oscillator Clock
to Baud
Generator Logic
V
CC
Crystal
Oscillator Clock
to Baud
Generator Logic
RX2
V
CC
C1
R
P
C2
XTAL1 XTAL1
XTAL2
XTAL2
TYPICAL CRYSTAL OSCILLATOR NETWORK
CRYSTAL
R
P
RX2 C1 C2
3.1 MHz 1 MΩ 1.5 kΩ
10 − 30 pF 40 − 60 pF
1.8 MHz 1 MΩ 1.5 kΩ 10 −30 pF 40 −60 pF
Figure 24. Typical Clock Circuits