Datasheet

TL16C552A, TL16C552AM
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
Active
IOR
(RD RBR)
CLK
Sample
SIN
(first byte)
Stop
t
d9
(see Note B )
RXRDY
t
pd8
(see Note A)
50%
50%
50%
NOTES: A. This is the reading of the last byte in the FIFO.
B. If FCR0 = 1, t
d9
= 3 RCLK cycles. For a time-out interrupt, t
d9
= 8 RCLK cycles.
Figure 12. Receiver Ready Mode 0 Waveforms
Active
IOR
(RD RBR)
CLK
Sample
Stop
t
d9
(see Note B)
RXRDY
t
pd8
SIN
(first byte that reaches
the trigger level)
(see Note A)
50%
50%
50%
NOTES: A. This is the reading of the last byte in the FIFO.
B. If FCR0–1, t
d9
= 3 RCLK cycles. For a trigger change level interrupt, t
d9
= 8 RCLK.
Figure 13. Receiver Ready Mode 1 Waveforms