Datasheet
FIFO Control Register (FCR)
TL16C550D , , TL16C550DI
www.ti.com
.................................................................................................................................................. SLLS597E – APRIL 2004 – REVISED DECEMBER 2008
Table 3. Summary of Accessible Registers
REGISTER ADDRESS
0DLAB =
0DLAB = 0 1DLAB = 0 2 2 3 4 5 6 7 0DLAB = 1 1DLAB = 1
0
Receiver
BIT
Transmitter Interrupt FIFO
Buffer Interrupt Line Modem Modem
NO.
Holding Indent. Control Line Status Scratch Divisor Latch
Register Enable Control Control Status
Register Register Register Register Register Latch (LSB) (MSB)
(Read Register Register Register Register
(Write Only) (Read Only) (Write Only)
Only)
RBR THR IER IIR FCR LCR MCR LSR MSR SCR DLL DLM
Enable
Received Word
Delta Clear
Data Bit Data 0 if Interrupt Length Data Terminal Data Ready
0 Data Bit 0 FIFO Enable to Send Bit 0 Bit 0 Bit 8
0
(1)
Available Pending Select Bit Ready (DR)
( Δ CTS)
Interrupt 0 (WLS0)
(ERBI)
Enable
Transmitter
Word
Holding Delta Data
Interrupt ID Receiver Length Request to Overrun
1 Data Bit 1 Data Bit 1 Register Set Ready Bit 1 Bit 1 Bit 9
Bit 1 FIFO Reset Select Bit Send (RTS) Error (OE)
Empty ( Δ DSR)
1 (WLS1)
Interrupt
(ETBEI)
Enable
Trailing
Receiver Number of
Interrupt ID Transmitter Parity Error Edge Ring
2 Data Bit 2 Data Bit 2 Line Status Stop Bits OUT1 Bit 2 Bit 2 Bit 10
Bit 2 FIFO Reset (PE) Indicator
Interrupt (STB)
(TERI)
(ELSI)
Enable
Delta Data
Modem Parity
Interrupt ID DMA Mode Framing Carrier
3 Data Bit 3 Data Bit 3 Status Enable OUT2 Bit 3 Bit 3 Bit 11
Bit 3
(2)
Select Error (FE) Detect
Interrupt (PEN)
( Δ DCD)
(EDSSI)
Even
Parity Break Clear to
4 Data Bit 4 Data Bit 4 0 0 Reserved Loop Bit 4 Bit 4 Bit 12
Select Interrupt Send (CTS)
(EPS)
Transmitter
Autoflow Data Set
Stick Holding
5 Data Bit 5 Data Bit 5 0 0 Reserved Control Enable Ready Bit 5 Bit 5 Bit 13
Parity Register
(AFE) (DSR)
(THRE)
Receiver Transmitter Ring
FIFOs Break
6 Data Bit 6 Data Bit 6 0 Trigger 0 Empty Indicator Bit 6 Bit 6 Bit 14
Enabled
(2)
Control
(LSB) (TEMT) (RI)
Divisor
Receiver Error in Data Carrier
Latch
7 Data Bit 7 Data Bit 7 0 Trigger 0 RCVR Detect Bit 7 Bit 7 Bit 15
Access Bit
(MSB) FIFO
(2)
(DCD)
(DLAB)
(1) Bit 0 is the least significant bit. It is the first bit serially transmitted or received.
(2) These bits are always 0 in the TL16C450 mode.
The FCR is a write-only register at the same location as the IIR, which is a read-only register. The FCR enables
and clears the FIFOs, sets the receiver FIFO trigger level, and selects the type of DMA signaling.
• Bit 0: This bit, when set, enables the transmitter and receiver FIFOs. Bit 0 must be set when other FCR bits
are written to or they are not programmed. Changing this bit clears the FIFOs.
• Bit 1: This bit, when set, clears all bytes in the receiver FIFO and clears its counter. The shift register is not
cleared. The 1 that is written to this bit position is self-clearing.
• Bit 2: This bit, when set, clears all bytes in the transmit FIFO and clears its counter. The shift register is not
cleared. The 1 that is written to this bit position is self-clearing.
• Bit 3: When FCR0 is set, setting FCR3 causes RXRDY and TXRDY to change from level 0 to level 1.
• Bits 4 and 5: These two bits are reserved for future use.
• Bits 6 and 7: These two bits set the trigger level for the receiver FIFO interrupt (see Table 4 ).
Copyright © 2004 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 33
Product Folder Link(s): TL16C550D TL16C550DI