Datasheet

Programmable Baud Generator
TL16C550D , , TL16C550DI
www.ti.com .................................................................................................................................................. SLLS597E – APRIL 2004 – REVISED DECEMBER 2008
• Bit 7: This bit is the complement of the data carrier detect ( DCD) input. When the ACE is in the diagnostic test
mode (LOOP [MCR4] = 1), this bit is equal to the MCR bit 3 (OUT2).
The ACE contains a programmable baud generator that takes a clock input in the range between dc and 16 MHz
and divides it by a divisor in the range between 1 and (2
16
– 1). The output frequency of the baud generator is
sixteen times (16 × ) the baud rate. The formula for the divisor is:
divisor = XIN frequency input ÷ (desired baud rate × 16)
Two 8-bit registers, called divisor latches, store the divisor in a 16-bit binary format. These divisor latches must
be loaded during initialization of the ACE in order to ensure desired operation of the baud generator. When either
of the divisor latches is loaded, a 16-bit baud counter is also loaded to prevent long counts on initial load.
Table 9 and Table 10 illustrate the use of the baud generator with crystal frequencies of 1.8432 MHz and 3.072
MHz respectively. For baud rates of 38.4 kbits/s and below, the error obtained is small. The accuracy of the
selected baud rate is dependent on the selected crystal frequency (see Figure 27 for examples of typical clock
circuits).
Table 9. Baud Rates Using a 1.8432-MHz Crystal
DIVISOR USED PERCENT ERROR
DESIRED
TO GENERATE DIFFERENCE BETWEEN
BAUD RATE
16 × CLOCK DESIRED AND ACTUAL
50 2304
75 1536
110 1047 0.026
134.5 857 0.058
150 768
300 384
600 192
1200 96
1800 64
2000 58 0.69
2400 48
3600 32
4800 24
7200 16
9600 12
19200 6
38400 3
56000 2 2.86
Table 10. Baud Rates Using a 3.072-MHz Crystal
DIVISOR USED PERCENT ERROR
DESIRED
TO GENERATE DIFFERENCE BETWEEN
BAUD RATE
16 × CLOCK DESIRED AND ACTUAL
50 3840
75 2560
110 1745 0.026
134.5 1428 0.034
150 1280
300 640
600 320
1200 160
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