Datasheet

THS8200
www.ti.com SLES032D –JUNE 2002–REVISED JUNE 2013
Finally, there is a digital output port with data encoded according to ITU-R.BT656. This is a loop-through
of the original input bus, prior to any THS8200 internal processing, and thus only provides standard data
when input to the THS8200 is provided in a 10-bit ITU-R BT.656 format. This output bus could be used to
connect to a separate NTSC/PAL video encoder. The data_clk656_on register activates the clock output
on this bus and the data_tristate656 register disables the output bus. It is recommended to disable this
output when not in use.
4.10 Power Down
THS8200 implements two power-down modes: dac_pwdn powers down the DAC channels but keeps all
digital logic active; chip_pwdn powers down the digital logic except the I
2
C interface. Activating both
registers enforces a complete analog/digital power down except for the I
2
C interface.
4.11 CGMS Insertion
The THS8200 can embed data within the vertical blanking interval, encoded according to the EIA-805 data
insertion standard. CGMS is an implementation of the EIA-805 standard that defines data insertion in
component video interface (CVI) video signals.
The THS8200 supports CGMS data insertion on line 41 of every frame in the 525P format. The data is
inserted on the Y channel only; Pb and Pr channels remain at the blanking level. CGMS data insertion is
enabled by activating the cgms_en register and programming the cgms_header and cgms_payload
registers appropriately. The user needs to program header and payload data in the correct format, as no
additional data encoding is done prior to insertion into the analog DAC output. The THS8200 only
performs a play-out function for the programmed data. The CGMS encoding block assumes that a full 10-
bit video range is used to determine the 70% of peak-white amplitude of a logic 1 bit, as prescribed by
EIA-805. The CSM does not affect the amplitude of the CGMS data insertion.
CGMS is inserted on line 41 as prescribed by EIA 770 standards for progressive format display of SDTV.
Fourteen bits can be inserted on this line, consisting of 6 bits header and 8 bits payload. The user can
directly program these bits into the corresponding THS8200 registers. Care should be taken to format this
data according to CGMS semantics; the user is referred to the original standards to determine
header/payload data programming. To avoid the transmission of invalid data, the data transmitted is
updated only when the CGMS register with the highest subaddress is programmed with cgms_en active.
CGMS insertion is possible in either 1x or 2x interpolated video modes of the THS8200. While EIA-805
allows the inserted data to change on every frame, and also allows data packets that would span multiple
lines (and therefore also multiple frames, since only 1 line/frame is used for insertion), the THS8200 does
not support multiline data insertion because it is not required for CGMS.
4.12 I
2
C Interface
The THS8200 contains a slave-only I
2
C interface on which both write and read are supported. The register
map shows which registers support read/write (R/W) and which are read-only (R). The device supports
normal and fast I
2
C modes (SCL up to 400 kHz). The I
2
C interface is also operational when no input clock
is received on CLKIN.
To discriminate between write and read operations, the device is addressed at separate device addresses.
There is an automatic internal sub-address increment counter to efficiently write/read multiple bytes in the
register map during one write/read operation. Furthermore, bit1 of the I
2
C device address is dependent
upon the setting of the I2CA pin, as follows:
• If address-selecting pin I2CA = 0, then
– write address is 40h (0100 0000)
– read address is 41h (0100 0001)
• If address-selecting pin I2CA = 1, then
– write address is 42h (0100 0010)
– read address is 43h (0100 0011)
Copyright © 2002–2013, Texas Instruments Incorporated Detailed Functional Description 57
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