Datasheet

THS8200
www.ti.com SLES032D –JUNE 2002–REVISED JUNE 2013
2.2 Terminal Functions
Table 2-1. Terminal Functions
TERMINAL
I/O
(1)
DESCRIPTION
NAME NO.
ABPb 15 O Analog output of DAC2. See AGY.
ARPr 17 O Analog output of DAC3. See AGY.
Analog output of DAC1. With the proper setting of FSADJ<n>, this output is capable of driving
AG Y 13 O
1.3-V full scale into a 37.5-Ω load.
AVDD 11, 14, 18 PWR Analog power supply, nominal 3.3 V
AVSS 12, 16 PWR Analog ground
10-bit video data input port. All 10 bits or the 8 MSB of this port can be connected to the video
data source. In 30-bit mode, the B data of RGB, or the Cb data of YCbCr, should be connected
BCb[9:0] 21 - 30 I
to this port. In 10-bit input mode, this port is unused. In 20-bit input mode, this port is used for
CbCr input data.
Main clock input. Video input data on the GY[9:0]/BCb[9:0]/RCr[9:0] ports should be
CLKIN 3 I synchronized to CLKIN. Depending on the input data format, CLKIN is supplied to THS8200 at
1x or 2x the pixel clock frequency.
Compensation pin for the internal reference amplifier. A 0.1-µF capacitor should be connected
COMP1 10 P
between COMP1 and analog power supply AVDD.
Compensation pin for the internal reference amplifier. A 0.1-µF capacitor should be connected
COMP2 9 P
between COMP2 and analog power supply AVDD.
Video ITU-R.BT656-compliant clock output. This clock output is off by default and should be
D1CLKO 71 O
activated via an I
2
C register setting.
ITU-R.BT656 compliant video data output port. Only available when ITU-R.BT656 input format
DO[9:5] 65 - 69
O is used. Can be used to connect to external PAL/NTSC video encoder. This port is off by
DO[4:0] 73 - 77
default and should be activated via an I
2
C register setting.
DVDD 32, 59, 79 PWR Digital core power, nominal 1.8 V
DVSS 31, 58, 78 PWR Digital core ground
Field identification signal for interlaced video formats. In slave timing mode, this is an input from
FID 47 I the video data source. In master timing mode this signal is unused, as only progressive-scan
VESA formats are supported in master mode.
Full scale adjustment control 1. A resistor should be connected between FSADJ1 and analog
ground AGND to control the full-scale output current of the DAC output channels. Via the
data_fsadj I
2
C programming register, the user can select between two full-scale ranges,
FSADJ1 7 P
determined by FSADJ1 or FSADJ2.
For 700-mV video output (1 Vpp including sync), the nominal value is 2.99 kΩ ; for 1.0-Vpp
video output (1.3 Vpp including sync) output the nominal value is 2.08 kΩ.
FSADJ2 8 P Full scale adjustment control 2. See FSADJ1.
GND_DLL 2 PWR Ground of clock doubler. Should be connected to analog ground.
GND_IO 20, 45, 72 PWR I/O ring ground
10-bit video data input port. All 10 bits or the 8 MSB of this port can be connected to the video
GY[9:0] 48 - 57 I data source. The G data of RGB or the Y data of YCbCr should be connected to this port. Port
used in 10-bit mode for CbYCrY video input data; in 20-bit input mode for Y data.
Horizontal source synchronization. In slave timing mode, this is an input from the video data
HS_IN 43 I/O source. In master timing mode, this is an output to the video data source with programmable
timing and polarity, serving as a horizontal data qualification signal to the video source.
Horizontal sync output (to display). Irrespective of slave/master timing mode configuration, this
HS_OUT 61 O
is always an output with timing generated by the DTG.
12CA 5 I I
2
C device address LSB selection
N.C. 1, 80 I Manufacturing test input. Must be tied to GND for normal operation.
PBKG (VSS) 6 PWR Substrate ground. Should be connected to analog ground.
10-bit video data input port. All 10-bits or the 8 MSB of this port can be connected to the video
data source. In 30-bit mode, the R data of RGB or the Cr data of YCbCr should be connected to
RCr[9:0] 33 - 42 I
this port. In the 10- /20-bit input mode, this port is unused. For some input formats this port is
unused.
RESETB 60 I Software reset pin (active low). The minimum reset duration is 200 ns.
(1) I = input, O = output, B = bidirectional, PWR = power or ground, P = passive
Copyright © 2002–2013, Texas Instruments Incorporated Terminal Descriptions 11
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