Datasheet

THS7360
www.ti.com SLOS674 –JUNE 2010
ELECTRICAL CHARACTERISTICS: V
S+
= +3.3 V (continued)
At T
A
= +25°C, R
L
= 150 Ω to GND, Filter mode, and dc-coupled input/output, unless otherwise noted.
THS7360
TEST
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS LEVEL
(1)
POWER SUPPLY
Operating voltage 2.6 3.3 5.5 V B
V
IN
= 0 V, all channels on 18.8 24.5 29.5 mA A
V
IN
= 0 V, SD channels on, SF channels off 5.6 7.1 9 mA A
Total quiescent current, no load
V
IN
= 0 V, SD channels off, SF channels on 13.2 17.4 20.5 mA A
V
IN
= 0 V, all channels off, V
DISABLE
= 3 V 0.1 10 mA A
Power-supply rejection ratio
At dc 56 dB C
(PSRR)
LOGIC CHARACTERISTICS
V
IH
Disabled or Bypass engaged 1.6 1.4 V A
V
IL
Enabled or Bypass disengaged 0.75 0.6 V A
I
IH
Applied voltage = 3.3 V 1 mA C
I
IL
Applied voltage = 0 V 1 mA C
Disable time 150 ns C
Enable time 150 ns C
Bypass/filter switch time 15 ns C
Table 1. TRUTH TABLE: V
S+
= +3.3 V
(1)
FILTER 1 FILTER 2 BYPASS SF DESCRIPTION
0 0 0 Selects the standard definition filter (9.2 MHz) for the SF channels
0 1 0 Selects the enhanced definition filter (17 MHz) for the SF channels
1 0 0 Selects the high-definition filter (35 MHz) for the SF channels
1 1 0 Selects the full/true high-definition filter (70 MHz) for the SF channels
X X 1 Bypasses the filters for the SF channels
(1) The logic input pins default to a logic '0' condition when left floating.
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Link(s): THS7360