Datasheet


   
 
SLAS201A − DECEMBER 1999 − REVISED SEPTEMBER 2002
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
data interface and timing (continued)
CLK
D[13:0]
DAC
Output
(IOUT1 or
IOUT2)
t
w(LPH)
t
d(D)
0.1%
0.1%
50%
t
h(D)
Valid Data
t
su(D)
t
pd
t
s(DAC)
1/f
CLK
t
r(IOUT)
90%
10%
50% 50% 50% 50%
Figure 29. Timing Diagram
Table 1. Input Interface Modes
MODE 0 MODE 1
FUNCTION/MODE
MODE PIN CONNECTED TO
DGND
MODE PIN CONNECTED TO
DV
DD
Input code format Binary Twos complement
External
Digital in
Internal
Digital in
DV
DD
Figure 30. Digital Equivalent Input