Datasheet

THS4500
THS4501
www.ti.com SLOS350F –APRIL 2002–REVISED OCTOBER 2011
PRINTED CIRCUIT BOARD LAYOUT capacitance can add a pole and/or a zero below
TECHNIQUES FOR OPTIMAL 400 MHz that can affect circuit operation. Keep
PERFORMANCE resistor values as low as possible, consistent with
load driving considerations.
Achieving optimum performance with high frequency
• Connections to other wideband devices on the
amplifier-like devices in the THS4500 family requires
board may be made with short direct traces or
careful attention to PCB layout parasitic and external
through onboard transmission lines. For short
component types.
connections, consider the trace and the input to
Recommendations that optimize performance include:
the next device as a lumped capacitive load.
Relatively wide traces (50 mils to 100 mils, or 1.27
• Minimize parasitic capacitance to any ac ground
mm to 2.54 mm) should be used, preferably with
for all of the signal I/O pins. Parasitic capacitance
ground and power planes opened up around
on the output and input pins can cause instability.
them. Estimate the total capacitive load and
To reduce unwanted capacitance, a window
determine if isolation resistors on the outputs are
around the signal I/O pins should be opened in all
necessary. Low parasitic capacitive loads (less
of the ground and power planes around those
than 4 pF) may not need an R
S
since the
pins. Otherwise, ground and power planes should
THS4500 family is nominally compensated to
be unbroken elsewhere on the board.
operate with a 2-pF parasitic load. Higher parasitic
• Minimize the distance (< 0.25”, 6.35 mm) from the
capacitive loads without an R
S
are allowed as the
power-supply pins to high frequency 0.1-μF
signal gain increases (increasing the unloaded
decoupling capacitors. At the device pins, the
phase margin). If a long trace is required, and the
ground and power-plane layout should not be in
6-dB signal loss intrinsic to a doubly-terminated
close proximity to the signal I/O pins. Avoid
transmission line is acceptable, implement a
narrow power and ground traces to minimize
matched impedance transmission line using
inductance between the pins and the decoupling
microstrip or stripline techniques (consult an ECL
capacitors. The power supply connections should
design handbook for microstrip and stripline layout
always be decoupled with these capacitors.
techniques).
Larger (6.8 μF or more) tantalum decoupling
• A 50-Ω environment is normally not necessary
capacitors, effective at lower frequency, should
onboard, and in fact, a higher impedance
also be used on the main supply pins. These may
environment improves distortion as shown in the
be placed somewhat farther from the device and
distortion versus load plots. With a characteristic
may be shared among several devices in the
board trace impedance defined based onboard
same area of the PCB. The primary goal is to
material and trace dimensions, a matching series
minimize the impedance seen in the
resistor into the trace from the output of the
differential-current return paths.
THS4500 family is used as well as a terminating
• Careful selection and placement of external
shunt resistor at the input of the destination
components preserve the high-frequency
device.
performance of the THS4500 family. Resistors
• Remember also that the terminating impedance is
should be a very low reactance type.
the parallel combination of the shunt resistor and
Surface-mount resistors work best and allow a
the input impedance of the destination device: this
tighter overall layout. Metal-film and carbon
total effective impedance should be set to match
composition, axially-leaded resistors can also
the trace impedance. If the 6-dB attenuation of a
provide good high frequency performance. Again,
doubly-terminated transmission line is
keep the leads and PCB trace length as short as
unacceptable, a long trace can be
possible. Never use wirewound type resistors in a
series-terminated at the source end only. Treat
high-frequency application. Since the output pin
the trace as a capacitive load in this case. This
and inverting input pins are the most sensitive to
configuration does not preserve signal integrity as
parasitic capacitance, always position the
well as a doubly-terminated line. If the input
feedback and series output resistors, if any, as
impedance of the destination device is low, there
close as possible to the inverting input pins and
is some signal attenuation due to the voltage
output pins. Other network components, such as
divider formed by the series output into the
input termination resistors, should be placed close
terminating impedance.
to the gain-setting resistors. Even with a low
parasitic capacitance shunting the external
• Socketing a high-speed part such as the THS4500
resistors, excessively high resistor values can
family is not recommended. The additional lead
create significant time constants that can degrade
length and pin-to-pin capacitance introduced by
performance. Good axial metal-film or
the socket can create an extremely troublesome
surface-mount resistors have approximately
parasitic network that can make it almost
0.2 pF in shunt with the resistor. For resistor
impossible to achieve a smooth, stable frequency
values greater than 2.0 kΩ, this parasitic
response. Best results are obtained by soldering
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Product Folder Link(s): THS4500 THS4501