Datasheet

0
500
1000
1500
2000
2500
100 k 1 M 10 M 100 M 1 G
+
−
1.21 kΩ 1.21 kΩ
50 Ω
V
O
f − Frequency − Hz
− Powerdown Output Impedance −
Z
OPD
Ω
V
S
= ±15 V and ±5 V
PRINTED-CIRCUIT BOARD LAYOUT
POWER-DOWN REFERENCE PIN
THS3091
THS3095
www.ti.com ........................................................................................................................................ SLOS423G – SEPTEMBER 2003 – REVISED OCTOBER 2008
The recommended mode of operation is to tie the
REF pin to midrail, thus setting the enable/disable
thresholds to V
midrail
+ 2.0 V and V
midrail
+ 0.8 V
respectively.
POWER-DOWN THRESHOLD VOLTAGE LEVELS
SUPPLY REFERENCE PIN ENABLE DISABLE
VOLTAGE (V) VOLTAGE (V) LEVEL (V) LEVEL (V)
± 15, ± 5 0.0 2.0 0.8
± 15 2.0 4.0 2.8
± 15 – 2.0 0.0 – 1.2
± 5 1.0 3.0 1.8
± 5 – 1.0 1.0 – 0.2
+30 15 17 15.8
Figure 70. Power-Down Output Impedance vs
+10 5.0 7.0 5.8
Frequency
Note that if the REF pin is left unterminated, it will
float to the positive rail and will fall outside of the
As with most current feedback amplifiers, the internal
recommended operating range given above (V
S –
≤
architecture places some limitations on the system
VREF ≤ V
S+
– 4 V). As a result, it will no longer serve
when in power-down mode. Most notably is the fact
as a reliable reference for the PD pin and the
that the amplifier actually turns ON if there is a ± 0.7 V
enable/disable thresholds given above will no longer
or greater difference between the two input nodes
apply. If the PD pin is also left unterminated, it will
(V+ and V – ) of the amplifier. If this difference
also float to the positive rail and the device will be
exceeds ± 0.7 V, the output of the amplifier creates an
enabled. If balanced, split supplies are used ( ± Vs)
output voltage equal to approximately [(V+ – V – ) – 0.7
and the REF and PD pins are grounded, the device
V] × Gain. This also implies that if a voltage is applied
will be disabled.
to the output while in power-down mode, the V – node
voltage is equal to V
O(applied)
× R
G
/(R
F
+ R
G
). For low
gain configurations and a large applied voltage at the
TECHNIQUES FOR OPTIMAL
output, the amplifier may actually turn ON due to the
PERFORMANCE
aforementioned behavior.
Achieving optimum performance with a
The time delays associated with turning the device on
high-frequency amplifier, like the THS3091/5,
and off are specified as the time it takes for the
requires careful attention to board layout parasitic and
amplifier to reach either 10% or 90% of the final
external component types.
output voltage. The time delays are in the order of
microseconds because the amplifier moves in and out
Recommendations that optimize performance include:
of the linear mode of operation in these transitions.
• Minimize parasitic capacitance to any ac ground
for all of the signal I/O pins. Parasitic capacitance
on the output and input pins can cause instability.
OPERATION
To reduce unwanted capacitance, a window
around the signal I/O pins should be opened in all
In addition to the power-down pin, the THS3095
of the ground and power planes around those
features a reference pin (REF) which allows the user
pins. Otherwise, ground and power planes should
to control the enable or disable power-down voltage
be unbroken elsewhere on the board.
levels applied to the PD pin. In most split-supply
applications, the reference pin is connected to
• Minimize the distance [ < 0.25 inch (6,35 mm)]
ground. In either case, the user needs to be aware of
from the power supply pins to high-frequency
voltage-level thresholds that apply to the power-down
0.1- µ F and 100-pF decoupling capacitors. At the
pin. The tables below show examples and illustrate
device pins, the ground and power plane layout
the relationship between the reference voltage and
should not be in close proximity to the signal I/O
the power-down thresholds. In the table, the threshold
pins. Avoid narrow power and ground traces to
levels are derived by the following equations:
minimize inductance between the pins and the
decoupling capacitors. The power supply
PD ≤ REF + 0.8 V for disable
connections should always be decoupled with
PD ≥ REF + 2.0 V for enable
these capacitors. Larger (6.8 µ F or more)
where the usable range at the REF pin is
tantalum decoupling capacitors, effective at lower
frequency, should also be used on the main
V
S –
≤ V
REF
≤ (V
S+
– 4 V).
supply pins. These may be placed somewhat
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