Datasheet

TFP401A-EP
www.ti.com SLDS160A –MARCH 2009– REVISED JULY 2011
Time Staggered Pixel Output. This option works only in conjunction with the 2-pixel/clock mode (PIXS = high).
Setting STAG = low will time stagger the even and odd pixel output so as to reduce the amount of instantaneous
current surge from the power supply. Depending on the PCB layout and design this can help reduce the amount
of system ground bounce and power supply noise. The time stagger is such that in 2-pixel/clock mode the even
pixel is delayed from the latching edge of ODCK by 0.25 Tcip. (Tcip is the period of ODCK. The ODCK period is
2Tpix when in 2-pixel/clock mode.)
Depending on system constraints of output load, pixel rate, panel input architecture and board cost the TFP401A
drive strength and staggered pixel options allow flexibility to reduce system power-supply noise, ground bounce
and EMI.
Power Management. The TFP401A offers several system power management features.
The output driver power down (PDO = low) is an intermediate mode which offers several uses. During this mode,
all output drivers except SCDT and CTL1 are driven to a high-impedance state while the rest of the device
circuitry remains active
The TFP401A power down (PD = low) is a complete power down in that it powers down the digital core, the
analog circuitry, and output drivers. All output drivers are placed into a Hi-Z state. All inputs are disabled except
for the PD input. The TFP401A will not respond to any digital or analog inputs until PD is pulled high.
Both PDO and PD have internal pullups, so if left unconnected they default the TFP401A to normal operating
modes.
Sync Detect. The TFP401A offers an output, SCDT, to indicate link activity. The TFP401A monitors activity on
DE to determine if the link is active. When 2^18 clocks produced by an on-chip free running oscillator whose
frequency is around 10-15 MHz pass without a transition on DE, the TFP401A considers the link inactive and
SCDT is driven low. Hence SCDT goes low after the terminal count of the counter is reached that is 17~26 ms.
When SCDT is low, if 8 DE edges are detected within the terminal count of 2^18 clocks, the link is considered
active and SCDT goes high.
SCDT can be used to signal a system power management circuit to initiate a system power down when the link
is considered inactive. The SCDT can also be tied directly to the TFP401A PDO input to power down the output
drivers when the link is inactive. It is not recommended to use the SCDT to drive the PD input since, once in
complete power-down, the analog inputs are ignored and the SCDT state does not change. An external system
power management circuit to drive PD is preferred.
SYNC DETECT OPERATION
Some graphics card when in sleep/standby mode send characters that can make the DE toggle and make SCDT
high, hence in such applications, to robustly determine if the link is in active or inactive mode, it is recommended
that a sync signal like HSYNC can be used in addition to the SCDT. Timing format on the recovered HSYNC
signal can be used in addition to SCDT to determine if the link is receiving a valid video format.
In applications where PD is being pulsed (to save power while in sleep/standby mode) when the link is inactive,
and SCDT is used solely to determine the link activity, then in such cases SCDT should not be used until 25 ms
of signal and power application.
There is a rare possibility that SCDT can get stuck high on power up or removal of the DVI signal. For example:
If the power on a DVI distribution box sourcing the signal to the receiver is cycled rapidly (2-3 times/second),
then there is a small possibility, (1 in ~40-50 times) of cycling power that SCDT may be stuck high when the box
is powered off.
TI POWERPAD™ 100-TQFP PACKAGE
The TFP401A is packaged in TI's thermally enhanced PowerPAD™ 100TQFP packaging. The PowerPAD™
package is a 14 mm y 14 mm y 1 mm TQFP outline with 0.5-mm lead-pitch. The PowerPAD™ package has a
specially designed die mount pad that offers improved thermal capability over typical TQFP packages of the
same outline. The TI 100-TQFP PowerPAD™ package offers a back-side solder plane that connects directly to
the die mount pad for enhanced thermal conduction. Soldering the back side of the TFP401A to the application
board is not required thermally as the device power dissipation is well within the package capability when not
soldered. If traces or vias are located under the back side pad, they should be protected by suitable solder mask
or other assembly technique to prevent inadvertent shorting to the exposed back side pad.
Copyright © 2009–2011, Texas Instruments Incorporated 15