Datasheet

TAS5727
www.ti.com SLOS670 –NOVEMBER 2010
PLL INPUT PARAMETERS AND EXTERNAL FILTER COMPONENTS
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f
MCLKI
MCLK frequency 2.8224 24.576 MHz
MCLK duty cycle 40% 50% 60%
t
r
/
Rise/fall time for MCLK 5 ns
t
f(MCLK)
LRCLK allowable drift before LRCLK reset 4 MCLKs
External PLL filter capacitor C1 SMD 0603 X7R 47 nF
External PLL filter capacitor C2 SMD 0603 X7R 4.7 nF
External PLL filter resistor R SMD 0603, metal film 470 Ω
ELECTRICAL CHARACTERISTICS
DC Characteristics
T
A
= 25°, PVCC_x = 18 V, DVDD = AVDD = 3.3 V, R
L
= 8 Ω, BTL AD mode, f
S
= 48 kHz (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
I
OH
= –4 mA
V
OH
High-level output voltage A_SEL_FAULT and SDA 2.4 V
DVDD = 3 V
I
OL
= 4 mA
V
OL
Low-level output voltage A_SEL_FAULT and SDA 0.5 V
DVDD = 3 V
V
I
< V
IL
; DVDD = AVDD
I
IL
Low-level input current 75 mA
= 3.6V
V
I
> V
IH
; DVDD =
I
IH
High-level input current 75
(1)
mA
AVDD = 3.6V
Normal mode 49 68
3.3 V supply voltage (DVDD,
I
DD
3.3 V supply current mA
Reset (RESET = low,
AVDD)
23 38
PDN = high)
Normal mode 32 50
I
PVDD
Supply current No load (PVDD_x) mA
Reset (RESET = low,
3 8
PDN = high)
Drain-to-source resistance, LS T
J
= 25°C, includes metallization resistance 75
r
DS(on)
(2)
mΩ
Drain-to-source resistance, HS T
J
= 25°C, includes metallization resistance 75
I/O Protection
V
uvp
Undervoltage protection limit PVDD falling 7.2 V
V
uvp,hyst
Undervoltage protection limit PVDD rising 7.6 V
OTE
(3)
Overtemperature error 150 °C
Extra temperature drop
OTE
HYST
(3)
30 °C
required to recover from error
I
OC
Overcurrent limit protection 4.5 A
I
OCT
Overcurrent response time 150 ns
Internal pulldown resistor at the Connected when drivers are in the high-impedance state
R
PD
3 kΩ
output of each half-bridge to provide bootstrap capacitor charge.
(1) I
IH
for the PBTL pin has a maximum limit of 200 µA due to an internal pulldown on the pin.
(2) This does not include bond-wire or pin resistance.
(3) Specified by design
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