Datasheet

t
h1
t
su1
t
(edge)
t
su2
t
h2
SCLK
(Input)
LRCLK
(Input)
SDIN
T0026-04
t
r
t
f
TAS5727
www.ti.com SLOS670 –NOVEMBER 2010
SERIAL AUDIO PORTS SLAVE MODE
over recommended operating conditions (unless otherwise noted)
TEST
PARAMETER MIN TYP MAX UNIT
CONDITIONS
f
SCLKIN
Frequency, SCLK 32 × f
S
, 48 × f
S
, 64 × f
S
C
L
= 30 pF 1.024 12.288 MHz
t
su1
Setup time, LRCLK to SCLK rising edge 10 ns
t
h1
Hold time, LRCLK from SCLK rising edge 10 ns
t
su2
Setup time, SDIN to SCLK rising edge 10 ns
t
h2
Hold time, SDIN from SCLK rising edge 10 ns
LRCLK frequency 8 48 48 kHz
SCLK duty cycle 40% 50% 60%
LRCLK duty cycle 40% 50% 60%
SCLK
SCLK rising edges between LRCLK rising edges 32 64
edges
t
(edge)
SCLK
LRCLK clock edge with respect to the falling edge of SCLK –1/4 1/4
period
t
r
/t
f
Rise/fall time for SCLK/LRCLK 8 ns
Figure 2. Slave-Mode Serial Data-Interface Timing
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Link(s): TAS5727