Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLinear ICsLinear IC - Audio amplifier 2-channel (stereo) or 4-channel (Quad) Class D HTQFP 64 (10x10

FEATURES

DESCRIPTION

TAS5706A

TAS5706B

www.ti.com

.............................................................................................................................................SLOS606D–MARCH2009–REVISEDSEPTEMBER2009

20-WStereoDigitalAudioPowerAmplifierwithEQandDRC

Processing

•AudioInput/Output–AdaptiveBiquadCoefficientsforEQand

DRCFilters

–20-Wintoan8-ΩLoadFroman18-VSupply

–ProgrammableInputandOutputMixers

–TwoSerialAudioInputs(FourAudio

Channels)–AutomaticSample-RateDetectionand

CoefficientBanking

•TAS5706ASupports:

•GeneralFeatures

–2-ChBridgedOutputs(20W×2)

–SerialControlInterfaceOperationalWithout

•TAS5706BSupports:

MCLK

–2-ChBridgedOutputs(20W×2)

–Factory-TrimmedInternalOscillatorAvoids

–4-ChSingle-EndedOutputs(10W×4)

theNeedforExternalCrystal

–2-ChSingle-Ended+1-ChBridged(2.1

–SurfaceMount,64-Terminal,10-mm×

Mode)(10W×2+20W)

10-mmHTQFPPackage

•Supports32-kHz–192-kHzSampleRates

–ThermalandShort-CircuitProtection

(LJ/RJ/I

•ClosedLoopPowerStageArchitecture

–ImprovedPSRRReducesPowerSupply

TheTAS5706A/Bisa20-W,efficient,digitalaudio

PerformanceRequirements

poweramplifierfordrivingstereobridged-tied

–HigherDampingFactorProvidesfor

speakers.Twoserialdatainputsallowprocessingof

Tighter,MoreAccurateSoundWith

uptofourdiscreteaudiochannelsandseamless

ImprovedBassResponse

integrationtomostdigitalaudioprocessorsand

MPEGdecoders,acceptingawiderangeofinput

–ConstantOutputPowerOverVariationin

dataandclockrates.Afullyprogrammabledatapath

Supply

allowsthesechannelstoberoutedtotheinternal

•WidePVCCRangeFrom(10Vto26V)

speakerdriversoroutputviathesubwooferor

–NoSeparateSupplyRequiredforGate

headphonePWMoutputs.

Drive

TheTAS5706A/Bisaslave-onlydevicereceivingall

•HeadphonePWMOutputs

clocksfromexternalsources.TheTAS5706A/B

operatesata384-kHzswitchingratefor32-,48-,96-,

•SubwooferPWMOutputs

and192-kHzdata,andata352.8kHzswitchingrate

•AMInterferenceAvoidanceSupport

for44.1-,88.2-,and176.4-kHzdata.The8×

•Audio/PWMProcessing

oversamplingcombinedwiththefourth-ordernoise

shaperprovidesaflatnoisefloorandexcellent

–IndependentChannelVolumeControlsWith

dynamicrangefrom20Hzto20kHz.

48-dBto–79-dBRange—SoftMute(50%

DutyCycle)

–ProgrammableDynamicRangeControl

–7ProgrammableBiquadsforSpeaker

EqualizationforLeftandRightChannels

–4ProgrammableBiquadsforBass

Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexas

Instrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet.

2PurePathDigitalisatrademarkofTexasInstruments.

3Allothertrademarksarethepropertyoftheirrespectiveowners.

PRODUCTIONDATAinformationiscurrentasofpublicationdate.

ProductsconformtospecificationsperthetermsoftheTexas

Instrumentsstandardwarranty.Productionprocessingdoesnot

necessarilyincludetestingofallparameters.

TAS5706A is Not Recommended for New Designs

Summary of content (71 pages)

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TAS5706A is Not Recommended for New Designs TAS5706A TAS5706B www.ti.com.............................................................................................................................................
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TAS5706A TAS5706B TAS5706A is Not Recommended for New Designs SLOS606D – MARCH 2009 – REVISED SEPTEMBER 2009............................................................................................................................................. www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
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TAS5706A is Not Recommended for New Designs TAS5706A TAS5706B www.ti.com............................................................................................................................................. SLOS606D – MARCH 2009 – REVISED SEPTEMBER 2009 2 Single-Ended (SE) + 1 BTL Mode (TAS5706B Only) 3.
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TAS5706A TAS5706B TAS5706A is Not Recommended for New Designs SLOS606D – MARCH 2009 – REVISED SEPTEMBER 2009............................................................................................................................................. www.ti.com Single-Ended (SE) 4.0 Mode (TAS5706B Only) 3.
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TAS5706A is Not Recommended for New Designs TAS5706A TAS5706B www.ti.com.............................................................................................................................................
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TAS5706A TAS5706B TAS5706A is Not Recommended for New Designs SLOS606D – MARCH 2009 – REVISED SEPTEMBER 2009............................................................................................................................................. www.ti.com 64-PIN, HTQFP PACKAGE (TOP VIEW) PIN FUNCTIONS PIN NAME AGND TYPE NO. 57 58 AVCC (1) 5-V TOLERANT TERMINATION DESCRIPTION (2) P Analog ground for power stage P Analog power supply for power stage.
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TAS5706A is Not Recommended for New Designs TAS5706A TAS5706B www.ti.com............................................................................................................................................. SLOS606D – MARCH 2009 – REVISED SEPTEMBER 2009 PIN FUNCTIONS (continued) PIN NAME TYPE NO.
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TAS5706A TAS5706B TAS5706A is Not Recommended for New Designs SLOS606D – MARCH 2009 – REVISED SEPTEMBER 2009............................................................................................................................................. www.ti.com PIN FUNCTIONS (continued) PIN NAME TYPE NO. (1) 5-V TOLERANT TERMINATION (2) DESCRIPTION Pullup Reset, active-low. A system reset is generated by applying a logic low to this terminal.
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TAS5706A TAS5706B TAS5706A is Not Recommended for New Designs www.ti.com............................................................................................................................................. SLOS606D – MARCH 2009 – REVISED SEPTEMBER 2009 DISSIPATION RATINGS PACKAGE (1) DERATING FACTOR TA = 25°C POWER RATING TA = 45°C POWER RATING TA = 70°C POWER RATING 10-mm × 10-mm QFP 29 mW/°C 2.89 W 2.31 W 1.
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TAS5706A TAS5706B TAS5706A is Not Recommended for New Designs SLOS606D – MARCH 2009 – REVISED SEPTEMBER 2009............................................................................................................................................. www.ti.com ELECTRICAL CHARACTERISTICS DC Characteristics, TA = 25°C, PVCC_X, AVCC = 18 V, RL = 8 Ω (unless otherwise noted) PARAMETER TEST CONDITIONS VOH High-level output voltage 3.
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TAS5706A TAS5706B TAS5706A is Not Recommended for New Designs www.ti.com............................................................................................................................................. SLOS606D – MARCH 2009 – REVISED SEPTEMBER 2009 AC Characteristics, TA = 25°C, PVCC_X, AVCC = 18 V, AVDD, DVDD = 3.
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TAS5706A TAS5706B TAS5706A is Not Recommended for New Designs SLOS606D – MARCH 2009 – REVISED SEPTEMBER 2009............................................................................................................................................. www.ti.com SERIAL AUDIO PORTS SLAVE MODE over recommended operating conditions (unless otherwise noted) TEST CONDITIONS PARAMETER TYP 1.024 MAX UNIT 12.
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TAS5706A TAS5706B TAS5706A is Not Recommended for New Designs www.ti.com.............................................................................................................................................
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TAS5706A TAS5706B TAS5706A is Not Recommended for New Designs SLOS606D – MARCH 2009 – REVISED SEPTEMBER 2009............................................................................................................................................. www.ti.
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TAS5706A TAS5706B TAS5706A is Not Recommended for New Designs www.ti.com............................................................................................................................................. SLOS606D – MARCH 2009 – REVISED SEPTEMBER 2009 BACK-END ERROR (BKND_ERR) Control signal parameters over recommended operating conditions (unless otherwise noted) PARAMETER MIN tw(ER) Pulse duration, BKND_ERR active (active-low) tp(valid_high) Programmable.
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TAS5706A TAS5706B TAS5706A is Not Recommended for New Designs SLOS606D – MARCH 2009 – REVISED SEPTEMBER 2009............................................................................................................................................. www.ti.com HEADPHONE SELECT (HPSEL) PARAMETER tw(MUTE) Pulse duration, HPSEL active td(VOL) Soft volume update time t(SW) Switch-over time (1) MIN MAX 350 None See (1) 0.2 UNIT ns ms 1 ms Defined by rate setting.
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TAS5706A TAS5706B TAS5706A is Not Recommended for New Designs www.ti.com.............................................................................................................................................
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TAS5706A TAS5706B TAS5706A is Not Recommended for New Designs SLOS606D – MARCH 2009 – REVISED SEPTEMBER 2009............................................................................................................................................. www.ti.
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TAS5706A TAS5706B TAS5706A is Not Recommended for New Designs www.ti.com.............................................................................................................................................
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TAS5706A TAS5706B TAS5706A is Not Recommended for New Designs SLOS606D – MARCH 2009 – REVISED SEPTEMBER 2009............................................................................................................................................. www.ti.
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TAS5706A TAS5706B TAS5706A is Not Recommended for New Designs www.ti.com............................................................................................................................................. SLOS606D – MARCH 2009 – REVISED SEPTEMBER 2009 TYPICAL CHARACTERISTICS, SE CONFIGURATION (continued) EFFICIENCY vs OUTPUT POWER SUPPLY CURRENT vs TOTAL OUTPUT POWER 2.0 100 RL = 4 Ω 90 VCC = 18 V 80 1.
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TAS5706A TAS5706B TAS5706A is Not Recommended for New Designs SLOS606D – MARCH 2009 – REVISED SEPTEMBER 2009............................................................................................................................................. www.ti.com DETAILED DESCRIPTION POWER SUPPLY The digital portion of the chip requires 3.3 V, and the power stages can work from 10 V to 26 V. CLOCK, AUTO DETECTION, AND PLL The TAS5706A DAP is a slave device. It accepts MCLK, SCLK, and LRCLK.
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Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TAS5706A TAS5706B SDIN2 SDIN1 SDI 0x04 SDIN1L SDIN1R SDIN2L SDIN2R 6 4 3 2 1 0x20 R' Down Mix 0x21<3:0> L' SUB 2 BQ 7 BQ 7 BQ 0x21<9:8> (L'+R')/2 0x21<11> Bass Management RS LS RF LF 0x21<12> Vol6 0x0D Vol 4 0x0B Vol 3 0x0A Vol 2 0x09 Vol1 0x08 DRC2 drc2_ coeff Drc2_en drc1_ coeff Drc1_en Drc2_dis drc1_ coeff Drc1_en drc1_ coeff Drc1_en DRC1 drc1_ coeff Drc1_en Drc1_dis Noise Shaper
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TAS5706A TAS5706B TAS5706A is Not Recommended for New Designs SLOS606D – MARCH 2009 – REVISED SEPTEMBER 2009............................................................................................................................................. www.ti.com I2S Timing I2S timing uses LRCLK to define when the data being transmitted is for the left channel and when it is for the right channel. LRCLK is low for the left channel and high for the right channel.
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TAS5706A TAS5706B TAS5706A is Not Recommended for New Designs www.ti.com.............................................................................................................................................
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TAS5706A TAS5706B TAS5706A is Not Recommended for New Designs SLOS606D – MARCH 2009 – REVISED SEPTEMBER 2009............................................................................................................................................. www.ti.com Left-Justified Left-justified (LJ) timing uses LRCLK to define when the data being transmitted is for the left channel and when it is for the right channel. LRCLK is high for the left channel and low for the right channel.
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TAS5706A TAS5706B TAS5706A is Not Recommended for New Designs www.ti.com.............................................................................................................................................
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TAS5706A TAS5706B TAS5706A is Not Recommended for New Designs SLOS606D – MARCH 2009 – REVISED SEPTEMBER 2009............................................................................................................................................. www.ti.com Right-Justified Right-justified (RJ) timing uses LRCLK to define when the data being transmitted is for the left channel and when it is for the right channel. LRCLK is high for the left channel and low for the right channel.
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TAS5706A TAS5706B TAS5706A is Not Recommended for New Designs www.ti.com.............................................................................................................................................
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TAS5706A TAS5706B TAS5706A is Not Recommended for New Designs SLOS606D – MARCH 2009 – REVISED SEPTEMBER 2009............................................................................................................................................. www.ti.com I2C SERIAL CONTROL INTERFACE The TAS5706A DAP has a bidirectional I2C interface that compatible with the I2C (Inter IC) bus protocol and supports both 100-kHz and 400-kHz data transfer rates for single and multiple byte write and read operations.
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TAS5706A TAS5706B TAS5706A is Not Recommended for New Designs www.ti.com............................................................................................................................................. SLOS606D – MARCH 2009 – REVISED SEPTEMBER 2009 Supplying a subaddress for each subaddress transaction is referred to as random I2C addressing. The TAS5706A also supports sequential I2C addressing.
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TAS5706A TAS5706B TAS5706A is Not Recommended for New Designs SLOS606D – MARCH 2009 – REVISED SEPTEMBER 2009............................................................................................................................................. www.ti.com Single-Byte Read As shown in Figure 42, a single-byte data read transfer begins with the master device transmitting a start condition followed by the I2C device address and the read/write bit.
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TAS5706A TAS5706B TAS5706A is Not Recommended for New Designs www.ti.com............................................................................................................................................. SLOS606D – MARCH 2009 – REVISED SEPTEMBER 2009 Dynamic Range Control (DRC) The DRC scheme has a single threshold, offset, and slope (all programmable). There is one ganged DRC for the left/right channels and one DRC for the subwoofer channel.
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TAS5706A TAS5706B TAS5706A is Not Recommended for New Designs SLOS606D – MARCH 2009 – REVISED SEPTEMBER 2009............................................................................................................................................. www.ti.com Loudness Function The TAS5706A provides a direct form I biquad for loudness on the subwoofer channel.
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TAS5706A is Not Recommended for New Designs TAS5706A TAS5706B www.ti.com............................................................................................................................................. SLOS606D – MARCH 2009 – REVISED SEPTEMBER 2009 b0 x(n) S b1 z a1 –1 z b2 z y(n) Magnitude Truncation –1 a2 –1 z –1 M0012-02 Figure 47.
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TAS5706A TAS5706B TAS5706A is Not Recommended for New Designs SLOS606D – MARCH 2009 – REVISED SEPTEMBER 2009............................................................................................................................................. www.ti.com BANK SWITCHING The TAS5706A uses an approach called bank switching together with automatic sample-rate detection. All processing features that must be changed for different sample rates are stored internally in the TAS5706A.
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TAS5706A TAS5706B TAS5706A is Not Recommended for New Designs www.ti.com............................................................................................................................................. SLOS606D – MARCH 2009 – REVISED SEPTEMBER 2009 APPLICATION INFORMATION Recovery From Error Protection Mechanisms in the TAS5706A/B • SCP (short-circuit protection, OCP) protects against shorts across the load, to GND, and to PVCC. • OTP turns off the device if Tdie (typical) > 150°C.
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TAS5706A TAS5706B TAS5706A is Not Recommended for New Designs SLOS606D – MARCH 2009 – REVISED SEPTEMBER 2009............................................................................................................................................. www.ti.com Calculation of Output Signal Level of TAS5706A/B Feedback Power Stage (Gain Is independent of PVCC) The gain of the TAS5706A/B is the total digital gain of the controller multiplied by the gain of the power stage.
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TAS5706A is Not Recommended for New Designs TAS5706A TAS5706B www.ti.com............................................................................................................................................. SLOS606D – MARCH 2009 – REVISED SEPTEMBER 2009 I2C SERIAL CONTROL COMMAND CHARACTERISTICS The DAP has two groups of I2C commands. One set is commands that are designed specifically to be operated while audio is streaming and that have built-in mechanisms to prevent noise, clicks, and pops.
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TAS5706A TAS5706B TAS5706A is Not Recommended for New Designs SLOS606D – MARCH 2009 – REVISED SEPTEMBER 2009............................................................................................................................................. www.ti.com 10. This completes the initialization sequence. From this step on, no further constraints are imposed on PDN, MUTE, and clocks. 11. During normal operation the user may do the following: a.
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TAS5706A is Not Recommended for New Designs TAS5706A TAS5706B www.ti.com............................................................................................................................................. SLOS606D – MARCH 2009 – REVISED SEPTEMBER 2009 Table 2. Serial Control Interface Register Summary (continued) SUBADDRESS NO.
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TAS5706A TAS5706B TAS5706A is Not Recommended for New Designs SLOS606D – MARCH 2009 – REVISED SEPTEMBER 2009............................................................................................................................................. www.ti.com Table 2. Serial Control Interface Register Summary (continued) SUBADDRESS 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 0x34 42 REGISTER NAME ch1_bq[3] ch1_bq[4] ch1_bq[5] ch1_bq[6] ch2_bq[0] ch2_bq[1] ch2_bq[2] ch2_bq[3] ch2_bq[4] NO.
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TAS5706A is Not Recommended for New Designs TAS5706A TAS5706B www.ti.com............................................................................................................................................. SLOS606D – MARCH 2009 – REVISED SEPTEMBER 2009 Table 2. Serial Control Interface Register Summary (continued) SUBADDRESS 0x35 0x36 0x37 0x38 NO.
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TAS5706A TAS5706B TAS5706A is Not Recommended for New Designs SLOS606D – MARCH 2009 – REVISED SEPTEMBER 2009............................................................................................................................................. www.ti.com CLOCK CONTROL REGISTER (0x00) In the manual mode, the clock control register provides a way for the system microprocessor to update the data and clock rates based on the sample rate and associated clock frequencies.
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TAS5706A TAS5706B TAS5706A is Not Recommended for New Designs www.ti.com............................................................................................................................................. SLOS606D – MARCH 2009 – REVISED SEPTEMBER 2009 ERROR STATUS REGISTER (0x02) Note that the error bits are sticky bits that are not cleared by the hardware. This means that the software must clear the register (write zeroes) and then read them to determine if there are any persistent errors.
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TAS5706A TAS5706B TAS5706A is Not Recommended for New Designs SLOS606D – MARCH 2009 – REVISED SEPTEMBER 2009............................................................................................................................................. www.ti.com Table 7.
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TAS5706A is Not Recommended for New Designs TAS5706A TAS5706B www.ti.com............................................................................................................................................. SLOS606D – MARCH 2009 – REVISED SEPTEMBER 2009 Bit D3 defines which volume register is used to control the volume of the HP_PWMx outputs when in headphone mode. When set to 0, the HP volume register (0x0C) controls the volume of the headphone outputs when in headphone mode.
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TAS5706A TAS5706B TAS5706A is Not Recommended for New Designs SLOS606D – MARCH 2009 – REVISED SEPTEMBER 2009............................................................................................................................................. www.ti.com VOLUME REGISTERS (0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D) Step size is 0.5 dB.
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TAS5706A TAS5706B TAS5706A is Not Recommended for New Designs www.ti.com............................................................................................................................................. SLOS606D – MARCH 2009 – REVISED SEPTEMBER 2009 MODULATION LIMIT REGISTER (0x10) Set modulation limit. See the appropriate power stage data sheet for recommended modulation limits. Table 12.
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TAS5706A TAS5706B TAS5706A is Not Recommended for New Designs SLOS606D – MARCH 2009 – REVISED SEPTEMBER 2009............................................................................................................................................. www.ti.com PWM SHUTDOWN GROUP REGISTER (0x19) Settings of this register determine which PWM channels are active. The default is 0x30 for two BTL output channels. The functionality of this register is tied to the state of bit D5 in the system control register.
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TAS5706A is Not Recommended for New Designs TAS5706A TAS5706B www.ti.com............................................................................................................................................. SLOS606D – MARCH 2009 – REVISED SEPTEMBER 2009 START/STOP PERIOD REGISTER (0x1A) This register is used to control the soft-start and soft-stop period when starting up or shutting down channels. The value in this register determines the time for which the PWM inputs switch at 50% duty cycle.
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TAS5706A TAS5706B TAS5706A is Not Recommended for New Designs SLOS606D – MARCH 2009 – REVISED SEPTEMBER 2009............................................................................................................................................. www.ti.com OSCILLATOR TRIM REGISTER (0x1B) The TAS5706A PWM processor contains an internal oscillator for PLL reference. This reduces system cost because an external reference is not required. Currently, TI recommends a trim resistor value of 18.2 kΩ (1%).
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TAS5706A TAS5706B TAS5706A is Not Recommended for New Designs www.ti.com............................................................................................................................................. SLOS606D – MARCH 2009 – REVISED SEPTEMBER 2009 INPUT MULTIPLEXER REGISTER (0x20) The hex value for each nibble is the channel number. For each input multiplexer, any input from SDIN1, SDIN2 can be mapped to any internal TAS5706A channel. Table 19.
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TAS5706A TAS5706B TAS5706A is Not Recommended for New Designs SLOS606D – MARCH 2009 – REVISED SEPTEMBER 2009............................................................................................................................................. www.ti.com Table 19.
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TAS5706A TAS5706B TAS5706A is Not Recommended for New Designs www.ti.com.............................................................................................................................................
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TAS5706A TAS5706B TAS5706A is Not Recommended for New Designs SLOS606D – MARCH 2009 – REVISED SEPTEMBER 2009............................................................................................................................................. www.ti.com AM MODE REGISTER (0x22) See the PurePath Digital™ AM Interference Avoidance application note (SLEA040). Table 21.
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TAS5706A is Not Recommended for New Designs TAS5706A TAS5706B www.ti.com............................................................................................................................................. SLOS606D – MARCH 2009 – REVISED SEPTEMBER 2009 PWM OUTPUT MUX REGISTER (0x25) This DAP output mux selects which internal PWM channel is output to the external pins. Any channel can be output to any external output pin.
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TAS5706A TAS5706B TAS5706A is Not Recommended for New Designs SLOS606D – MARCH 2009 – REVISED SEPTEMBER 2009............................................................................................................................................. www.ti.com Table 24.
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TAS5706A TAS5706B TAS5706A is Not Recommended for New Designs www.ti.com............................................................................................................................................. SLOS606D – MARCH 2009 – REVISED SEPTEMBER 2009 LOUDNESS BIQUAD GAIN INVERSE REGISTER (0x26) Bit D6 of the volume configuration register (0x0E) enables/disables gain compensation for BQ1. D6 = 0 disables gain compensation (default); D6 = 1 enables gain compensation. Max/min biquad gain = ±4.
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TAS5706A TAS5706B TAS5706A is Not Recommended for New Designs SLOS606D – MARCH 2009 – REVISED SEPTEMBER 2009............................................................................................................................................. www.ti.com TAS5706B SPECIFIC REGISTER SETTINGS: The TAS5706B is recommended for 2.1-mode operations. When used in the 2.1 mode, the following register settings are recommended for best performance: Shutdown Group Register Table 28.
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TAS5706A is Not Recommended for New Designs TAS5706A TAS5706B www.ti.com............................................................................................................................................. SLOS606D – MARCH 2009 – REVISED SEPTEMBER 2009 Table 30.
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TAS5706A TAS5706B TAS5706A is Not Recommended for New Designs SLOS606D – MARCH 2009 – REVISED SEPTEMBER 2009............................................................................................................................................. www.ti.com Inter Channel Delay Registers ICD (Inter Channel Delay) Register values have to be updated when used in 2.1 Mode. NOTE: Please contact Factory to get the optimized ICD Register Values.
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TAS5706A is Not Recommended for New Designs TAS5706A TAS5706B www.ti.com............................................................................................................................................. SLOS606D – MARCH 2009 – REVISED SEPTEMBER 2009 Changes from Revision C (March 2009) to Revision D ..................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties.
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PACKAGE MATERIALS INFORMATION www.ti.com 30-May-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TAS5706APAPR HTQFP PAP 64 1000 330.0 24.4 13.0 13.0 1.5 16.0 24.0 Q2 TAS5706BPAPR HTQFP PAP 64 1000 330.0 24.4 13.0 13.0 1.5 16.0 24.
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PACKAGE MATERIALS INFORMATION www.ti.com 30-May-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TAS5706APAPR HTQFP PAP 64 1000 367.0 367.0 45.0 TAS5706BPAPR HTQFP PAP 64 1000 367.0 367.0 45.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.