Datasheet

TAS5631
SLES221C –JULY 2009–REVISED APRIL 2010 www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
PVDD_X = 50V, GVDD_X = 12 V, VDD = 12V, T
C
(case temperature) = 75°C, f
S
= 384 kHz, unless otherwise specified.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
I/O PROTECTION
V
uvp,G
Undervoltage protection limit, GVDD_X 10 V
V
uvp,hyst
(1)
0.6 V
OTW1
(1)
Overtemperature warning 1 95 100 105 °C
OTW2
(1)
Overtemperature warning 2 115 125 135 °C
Temperature drop needed below OTW
OTW
hyst
(1)
temperature for OTW to be inactive after 25 °C
OTW event
Overtemperature error 145 155 165 °C
OTE
(1)
OTE-OTW differential 30 °C
A reset must occur for SD to be released
OTE
HYST
(1)
25 °C
following an OTE event
OLPC Overload protection counter f
PWM
= 384 kHz 2.6 ms
Resistor – programmable, nominal peak
current in 1-Ω load,
19 A
64-pin QFP package (PHD)
R
OCP
= 22 kΩ
Overcurrent limit response
Resistor – programmable, nominal peak
current in 1-Ω load,
I
OC
19 A
44-pin PSOP3 package (DKD)
R
OCP
= 24 kΩ
Resistor – programmable, nominal peak
current in 1-Ω load,
Overcurrent response time, latched 19 A
R
OCP
= 47 kΩ
Time from application of short condition to
I
OCT
Overcurrent response time 150 ns
Hi-Z of affected half-bridge
Connected when RESET is active to
Internal pulldown resistor at output of each
I
PD
provide bootstrap charge. Not used in SE 3 mA
half-bridge
mode.
STATIC DIGITAL SPECIFICATIONS
V
IH
High-level input voltage 1.9 V
INPUT_X, M1, M2, M3, RESET
V
IL
Low-level input voltage 1.45 V
I
lkg
Input leakage current 100 mA
OTW/SHUTDOWN (SD)
Internal pullup resistance, OTW1 to VREG,
R
INT_PU
20 26 33 kΩ
OTW2 to VREG, SD to VREG
Internal pullup resistor 3 3.3 3.6
V
OH
High-level output voltage V
External pullup of 4.7 kΩ to 5 V 4.5 5
V
OL
Low-level output voltage I
O
= 4 mA 200 500 mV
Device fanout OTW1, OTW2, SD, CLIP,
FANOUT No external pullup 30 devices
READY
(1) Specified by design
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Not Recommended For New Designs