Datasheet

TAS5630B
www.ti.com SLES217C –NOVEMBER 2010–REVISED SEPTEMBER 2012
ELECTRICAL CHARACTERISTICS (continued)
PVDD_X = 50 V, GVDD_X = 12 V, VDD = 12 V, T
C
(Case temperature) = 75°C, f
S
= 400 kHz, unless otherwise specified.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
I/O PROTECTION
Undervoltage protection limit, GVDD_x and
V
uvp,G
9.5 V
VDD
V
uvp,hyst
(1)
0.6 V
OTW1
(1)
Overtemperature warning 1 95 100 105 °C
OTW2
(1)
Overtemperature warning 2 115 125 135 °C
Temperature drop needed below OTW
OTW
hyst
(1)
temperature for OTW to be inactive after 25 °C
OTW event
Overtemperature error 145 155 165 °C
OTE
(1)
OTE-OTW differential 30 °C
A reset must occur for SD to be released
OTE
hyst
(1)
25 °C
following an OTE event.
OLPC Overload protection counter f
PWM
= 400 kHz 2.6 ms
Resistor – programmable, nominal peak
current in 1-Ω load,
15 A
64-pin QFP package (PHD)
R
OCP
= 22 kΩ
Overcurrent limit protection
Resistor – programmable, nominal peak
I
OC
current in 1-Ω load,
15 A
44-Pin PSOP3 package (DKD),
R
OCP
= 24 kΩ
Resistor – programmable, nominal peak
current in 1-Ω load,
Overcurrent limit protection, latched 15 A
R
OCP
= 47 kΩ
Time from switching transition to flip-state
I
OCT
Overcurrent response time 150 ns
induced by overcurrent
Connected when RESET is active to
Internal pulldown resistor at output of each
I
PD
provide bootstrap charge. Not used in SE 3 mA
half-bridge
mode
STATIC DIGITAL SPECIFICATIONS
V
IH
High-level input voltage 2 V
M1, M2, M3, RESET
V
IL
Low-level input voltage 0.8 V
I
lkg
Input leakage current 100 μA
OTW/SHUTDOWN (SD)
Internal pullup resistance, OTW, OTW1,
R
INT_PU
20 26 32 kΩ
OTW2, CLIP, READY, SD to VREG
Internal pullup resistor 3 3.3 3.6
V
OH
High-level output voltage V
External pullup of 4.7 kΩ to 5 V 4.5 5
V
OL
Low-level output voltage I
O
= 4 mA 200 500 mV
Device fanout OTW, OTW1, OTW2, SD,
FANOUT No external pullup 30 devices
CLIP, READY
(1) Specified by design.
Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Links: TAS5630B