Datasheet

23
22
SCLK
32Clks
LRCLK
LeftChannel
24-BitMode
1
19 18
20-BitMode
16-BitMode
15
14
MSB LSB
32Clks
RightChannel
2-ChannelLeft-JustifiedStereoInput
T0034-02
4
5
9 8
1
4
5
1
0
0
0
23
22 1
19 18
15
14
MSB LSB
4
5
9 8
1
4
5
1
0
0
0
SCLK
TAS5548
SLES270 –NOVEMBER 2012 www.ti.com
7.8.2 Left-Justified Timing
Left-justified (LJ) timing uses LRCLK to define when the data being transmitted is for the left channel and when it
is for the right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at 64
f
S
is used to clock in the data. The first bit of data appears on the data lines at the same time LRCLK toggles.
The data is written MSB first and is valid on the rising edge of the bit clock. The TAS5548 masks unused trailing
data bit positions.
Figure 7-10. Left-Justified 64-f
S
Format
56 Electrical Specifications Copyright © 2012, Texas Instruments Incorporated
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