Datasheet

S
S
S
S
32
28
122
4
23
22
21
20
4
3
0
Overhead / Guard
Bits
16-Bit
Audio
18-Bit
Audio
20-Bit
Audio
24-Bit
Audio
Precision / Noise
Bits
TAS5548
www.ti.com SLES270 –NOVEMBER 2012
3.2.1 Digital Audio Processor (DAP) Arithmetic Unit
The digital audio processor (DAP) arithmetic unit is a fixed-point computational engine consisting of an
arithmetic unit and data and coefficient memory blocks.
The DAP arithmetic unit is used to implement all firmware functions - loudness compensation, bass and
treble processing, dynamic range control, channel filtering, input and output mixing.
Figure 3-5 shows the data word structure of the DAP arithmetic unit. Four bits of overhead or guard bits
are provided at the upper end of the 32-bit DAP word, and 4 bits of computational precision or noise bits
are provided at the lower end of the 32-bit word. The incoming digital audio words are all positioned with
the most significant bit abutting the 4-bit overhead/guard boundary. The sign bit in bit 31 indicates that all
incoming audio samples are treated as signed data samples.
Figure 3-5. DAP Arithmetic Unit Data Word Structure
The arithmetic engine is a 32-bit (9.23 format) processor consisting of a general-purpose 60-bit arithmetic
logic unit and function-specific arithmetic blocks. Multiply operations (excluding the function-specific
arithmetic blocks) always involve 32-bit (9.23) DAP words and 28-bit (5.23) coefficients (usually I2C
programmable coefficients). If a group of products are to be added together, the 60-bit product of each
multiplication is applied to a 60-bit adder, where a DSP-like multiply-accumulate (MAC) operation takes
place. Biquad filter computations use the MAC operation to maintain precision in the intermediate
computational stages.
To maximize the linear range of the 76-bit ALU, saturation logic is not used. In MAC computations,
intermediate overflows are permitted, and it is assumed that subsequent terms in the computation flow will
correct the overflow condition. The biquad filter structure used in the TAS5548 is the “direct form I”
structure and has only one accumulation node (for an example, see the Biquad section). With this type of
structure, intermediate overflow are allowable as long as the designer of the filters has assured that the
final output will bounded and not overflow. Figure 4.2-3 is an example, using 16-bit arithmetic for ease of
illustration, of a bounded computation that experiences intermediate overflow condition.
The DAP memory banks include a dual port data RAM for storing intermediate results, a coefficient RAM,
and a fixed program ROM. Only the coefficient RAM, assessable via the I2C bus, is available to the user.
Copyright © 2012, Texas Instruments Incorporated TAS5548 DAP Architecture 17
Submit Documentation Feedback
Product Folder Links: TAS5548