Datasheet

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7.1ClockControlRegister(0x00)
7.1.1MasterClockOutputDivider
TAS3108,TAS3108IA
AUDIODIGITALSIGNALPROCESSORS
SLES152B–OCTOBER2005–REVISEDNOVEMBER2007
Register0x00providestheuserwithcontroloverMCLK,LRCLK,SCLKOUT1,SCLKOUT2,data-word
size,andserialaudioportmodes.Register0x00default=0x01001B22.
Table7-1.ClockControlRegister(0x00)
D31D30D29D28D27D26D25D24DESCRIPTION
000NotUsed
W1W0Masterclockoutputdivider
Y2Y1Y0MastermodeLRCLKdivider
D23D22D21D20D19D18D17D16DESCRIPTION
ICSSCLKOUTselect(default=0)
IMSSAPmaster/slavemuxselect(1=mastermode,0=slavemode)
X2X1X0SCLKINandSCLKOUTclockdivide
Z2Z1Z0MCLK,SCLKratio(mastermodeonly)
D15D14D13D12D11D10D9D8DESCRIPTION
XXDon'tcare
XDon'tcare
IW1IW0Inputaudiodatawordsize
XDon'tcare
OW1OW0Outputaudiodatawordsize
D7D6D5D4D3D2D1D0DESCRIPTION
IM3IM2IM1IM0Inputdataformat
OM3OM2OM1OM0Outputdataformat
Bits28–27(W1andW0)definetheratiobetweenMCLKI(orthecrystalfrequency)andMCLKO.This
allowstheaccommodationofdevicesthatrequireanMCLK=128LRCLKanddevicesthatrequirean
MCLK=256LRCLK,withouthavingtousegluelogictodividethatclockdown.Thisbithasmeaning
whetherinclock-masterorclock-slavemode.
W1W0DESCRIPTION
00MCLKO=MCLKI
01MCLKO=MCLKI/2
10MCLKO=MCLKI/4
11MCLKO=MCLKI/4
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CRegisterMap
Not Recommended for New Designs