Not Recommended for New Designs TAS3108, TAS3108IA AUDIO DIGITAL SIGNAL PROCESSORS www.ti.com SLES152B – OCTOBER 2005 – REVISED NOVEMBER 2007 1 Introduction 1.
Not Recommended for New Designs TAS3108, TAS3108IA AUDIO DIGITAL SIGNAL PROCESSORS www.ti.com SLES152B – OCTOBER 2005 – REVISED NOVEMBER 2007 Contents 1 2 3 Introduction ............................................... 1 Features .............................................. 1 7.1 Clock Control Register (0x00) 1.2 Applications ........................................... 1 7.2 7.3 Status Register (0x02) .............................. 41 I2C Memory Load Control and Data Registers (0x04 and 0x05) .
Not Recommended for New Designs TAS3108, TAS3108IA AUDIO DIGITAL SIGNAL PROCESSORS www.ti.com SLES152B – OCTOBER 2005 – REVISED NOVEMBER 2007 2 Functional Description 2.1 Device Description The TAS3108 and TAS3108IA are fully programmable high-performance audio processors. The devices use an efficient, custom, multi-instruction programming environment optimized for digital audio processing algorithms.
Not Recommended for New Designs TAS3108, TAS3108IA AUDIO DIGITAL SIGNAL PROCESSORS www.ti.com SLES152B – OCTOBER 2005 – REVISED NOVEMBER 2007 2.2 Power Supply The power supply contains supply regulators that provide analog and digital regulated power for various sections of the TAS3108/TAS3108IA. Only one external 3.3-V supply is required. All other voltages are generated on-chip from the external 3.3-V supply. 2.
Not Recommended for New Designs www.ti.com TAS3108, TAS3108IA AUDIO DIGITAL SIGNAL PROCESSORS SLES152B – OCTOBER 2005 – REVISED NOVEMBER 2007 2.7 Audio DSP Core The audio DSP core arithmetic unit is a fixed-point computational engine consisting of an arithmetic unit and data and coefficient memory blocks.
Not Recommended for New Designs TAS3108, TAS3108IA AUDIO DIGITAL SIGNAL PROCESSORS www.ti.com SLES152B – OCTOBER 2005 – REVISED NOVEMBER 2007 3 Physical Characteristics 3.
Not Recommended for New Designs TAS3108, TAS3108IA AUDIO DIGITAL SIGNAL PROCESSORS www.ti.com SLES152B – OCTOBER 2005 – REVISED NOVEMBER 2007 3.2 Terminal Descriptions TERMINAL NAME NO. INPUT/ OUTPUT (1) AVDD 38 I AVSS 1 CS0 7 I DVDD 9, 30 I DVSS 10, 29 PULLUP/ PULLDOWN (2) DESCRIPTION Analog power supply (3.3 V) Analog ground Pulldown Chip select Digital power supply input (3.
Not Recommended for New Designs TAS3108, TAS3108IA AUDIO DIGITAL SIGNAL PROCESSORS www.ti.com SLES152B – OCTOBER 2005 – REVISED NOVEMBER 2007 As long as RESET is held LOW, the device is in the reset state. During reset, all I2C and serial data bus operations are ignored. The I2C interface SCL and SDA lines go into a high-impedance state and remain in that state until device initialization has completed.
Not Recommended for New Designs TAS3108, TAS3108IA AUDIO DIGITAL SIGNAL PROCESSORS www.ti.com SLES152B – OCTOBER 2005 – REVISED NOVEMBER 2007 longer driving the GPIO pin low after the load has completed (~100 ms following a reset if no EEPROM is present), the state of the GPIO pin can be observed. Then the system controller can access the TAS3108/TAS3108IA through the I2C interface and read the status register to determine the load status.
Not Recommended for New Designs TAS3108, TAS3108IA AUDIO DIGITAL SIGNAL PROCESSORS www.ti.com SLES152B – OCTOBER 2005 – REVISED NOVEMBER 2007 Table 3-2.
Not Recommended for New Designs TAS3108, TAS3108IA AUDIO DIGITAL SIGNAL PROCESSORS www.ti.com SLES152B – OCTOBER 2005 – REVISED NOVEMBER 2007 Following a reset, ensure that the clock register (0x00) is written before performing volume, treble, or bass updates. Commands to reconfigure the SAP can be accompanied by mute and unmute commands for quiet operation. However, care must be taken to ensure that the mute command has completed before the SAP is commanded to reconfigure.
Not Recommended for New Designs TAS3108, TAS3108IA AUDIO DIGITAL SIGNAL PROCESSORS www.ti.com SLES152B – OCTOBER 2005 – REVISED NOVEMBER 2007 3.8.2 2 Channel Left Justified Timing In 2 channel left justified timing, LRCLK is HIGH when left channel data is transmitted and LOW when right channel data is transmitted. SCLK is a bit clock running at 64 × fS which clocks in each bit of the data. The first bit of data appears on the data lines at the same time LRCLK toggles.
Not Recommended for New Designs TAS3108, TAS3108IA AUDIO DIGITAL SIGNAL PROCESSORS www.ti.com SLES152B – OCTOBER 2005 – REVISED NOVEMBER 2007 3.8.3 2 Channel Right Justified Timing In 2-channel right-justified timing, LRCLK is HIGH when left channel data is transmitted and LOW when right channel data is transmitted. SCLK is a bit clock running at 64 × fS, which clocks in each bit of the data. The first bit of data appears on the data lines 8 bit-clock periods (for 24-bit data) after LRCLK toggles.
Not Recommended for New Designs TAS3108, TAS3108IA AUDIO DIGITAL SIGNAL PROCESSORS www.ti.
Not Recommended for New Designs TAS3108, TAS3108IA AUDIO DIGITAL SIGNAL PROCESSORS www.ti.
Not Recommended for New Designs TAS3108, TAS3108IA AUDIO DIGITAL SIGNAL PROCESSORS www.ti.com SLES152B – OCTOBER 2005 – REVISED NOVEMBER 2007 3.8.5 SAP Input to SAP Output—Processing Flow All SAP data format options other than I2S result in a two-sample delay from input to output, as shown in Figure 3-7. If I2S formatting is used for both the input SAP and the output SAP, the polarity of LRCLK in Figure 3-7 must be inverted.
Submit Documentation Feedback SDIN4 SDIN3 SDIN2 G E C A Serial Input Rx Holding Regs Regs H F D B H F D B Input Holding Regs Sample Time N G E C A Input Holding Regs Channel 3 Output Mux Input Mux Channel 3 Channel 2 Channel 1 Sample Time N + 1 Output Mux Sample Time N + 1 Input Mux Channel 2 Channel 1 Sample Time N + 1 Z Y X W V U Z Y X W V U Sample Time N + 2 Sample Time N + 2 SDOUT3 SDOUT2 SDOUT1 SDOUT3 SDOUT2 SDOUT1 SDIN4 SDIN3 SDIN2 SDIN1 SDI
Not Recommended for New Designs TAS3108, TAS3108IA AUDIO DIGITAL SIGNAL PROCESSORS www.ti.com SLES152B – OCTOBER 2005 – REVISED NOVEMBER 2007 4 Algorithm and Software Development Tools for TAS3108/TAS3108IA The TAS3108/TAS3108IA algorithm and software development tool set is a combination of classical development tools and graphical development tools. The tool set is used to build, debug, and execute programs in both the audio DSP and 8051 sections of the TAS3108/TAS3108IA.
Not Recommended for New Designs www.ti.com TAS3108, TAS3108IA AUDIO DIGITAL SIGNAL PROCESSORS SLES152B – OCTOBER 2005 – REVISED NOVEMBER 2007 5 Clock Controls Clock management for the TAS3108/TAS3108IA consists of two control structures: • Master clock management – Oversees the selection of the clock frequencies for the 8051 microprocessor, the I2C controller, and the audio DSP core – The master clock (MCLKI or XTALI) is the source for these clocks.
Not Recommended for New Designs TAS3108, TAS3108IA AUDIO DIGITAL SIGNAL PROCESSORS www.ti.com SLES152B – OCTOBER 2005 – REVISED NOVEMBER 2007 Table 5-1. PLL2, PLL1, and PLL0 Pin Configuration Controls PLL2 PLL1 PLL0 AUDIO DSP CLOCK 0 0 0 11 × MCLK/1 0 0 1 11 × MCLK/2 0 1 0 11 × MCLK/4 0 1 1 Reserved 1 X X Reserved Audio DSP clock or audio DSP clock/4 is used to clock the on-chip microprocessor. The input pin MICROCLK_DIV makes this clock choice.
Not Recommended for New Designs TAS3108, TAS3108IA AUDIO DIGITAL SIGNAL PROCESSORS www.ti.com SLES152B – OCTOBER 2005 – REVISED NOVEMBER 2007 Enable Mute and Wait for Completion RESET Pin = Low Change fMCLK No Are Clocks Stable? Yes RESET Pin = High After TAS3108/TAS3108IA Initializes, Re-initialize I2C Registers F0007-01 Figure 5-1.
Not Recommended for New Designs TAS3108, TAS3108IA AUDIO DIGITAL SIGNAL PROCESSORS www.ti.
Not Recommended for New Designs TAS3108, TAS3108IA AUDIO DIGITAL SIGNAL PROCESSORS www.ti.com SLES152B – OCTOBER 2005 – REVISED NOVEMBER 2007 PLL2 CRYSTAL MCLKO PLL1 PLL0 0 1 x 11 PLL 3 MUX MICROPROCESSOR CLOCK 1 ÷2 2 ÷4 Word Size Code IW2/OW2 IW1/OW1 IW0/OW0 0 0 X 1 0 X 0 1 X 1 1 X ÷4 Word Size 32-bit 16-bit 20-bit 24-bit MUX ÷2N 2 ÷4 AB MUX N[2:0] M[3:0] IW[2:0] OW[2:0] NOTE: Input and output word sizes are independent.
Not Recommended for New Designs TAS3108, TAS3108IA AUDIO DIGITAL SIGNAL PROCESSORS www.ti.com SLES152B – OCTOBER 2005 – REVISED NOVEMBER 2007 When the serial audio port (SAP) is in the master mode, the SAP uses the MCLKI or XTALI master clock to drive the serial port clocks SCLKOUT1, SLCKOUT2, and LRCLK. When the SAP is in the slave mode, LRCLK is an input and SCLKOUT2 and SCLKOUT1 are derived from SCLKIN.
Not Recommended for New Designs TAS3108, TAS3108IA AUDIO DIGITAL SIGNAL PROCESSORS www.ti.com SLES152B – OCTOBER 2005 – REVISED NOVEMBER 2007 Table 5-4. TAS3108/TAS3108IA MCLK and LRCLK Common Values (MCLK = 12.288 MHz or MCLK = 11.2896 MHz) fS Sample Rate (kHz) Ch per SDIN 32 2 MCLK/ LRCLK MCLK Freq Ratio (MHz) (× fS) SCLKIN Rate (× fS) SCLKIN Freq (MHz) 64 2.
Not Recommended for New Designs TAS3108, TAS3108IA AUDIO DIGITAL SIGNAL PROCESSORS www.ti.com SLES152B – OCTOBER 2005 – REVISED NOVEMBER 2007 Table 5-4. TAS3108/TAS3108IA MCLK and LRCLK Common Values (MCLK = 12.288 MHz or MCLK = 11.2896 MHz) (continued) fS Sample Rate (kHz) Ch per SDIN 192 2 MCLK/ LRCLK MCLK Freq Ratio (MHz) (× fS) 64 12.
Not Recommended for New Designs www.ti.com TAS3108, TAS3108IA AUDIO DIGITAL SIGNAL PROCESSORS SLES152B – OCTOBER 2005 – REVISED NOVEMBER 2007 6 Microprocessor Controller The 8051 microprocessor receives and distributes I2C write data, retrieves and outputs to the I2C bus controllers the required I2C read data, and participates in most processing tasks requiring multiframe processing cycles.
Not Recommended for New Designs TAS3108, TAS3108IA AUDIO DIGITAL SIGNAL PROCESSORS www.ti.
Not Recommended for New Designs TAS3108, TAS3108IA AUDIO DIGITAL SIGNAL PROCESSORS www.ti.
Not Recommended for New Designs TAS3108, TAS3108IA AUDIO DIGITAL SIGNAL PROCESSORS www.ti.com SLES152B – OCTOBER 2005 – REVISED NOVEMBER 2007 Table 6-2. Master Addresses BASE ADDRESS CS0 R/W MASTER ADDRESS 1010 00 0 0 0xA0 1010 00 0 1 0xA1 1010 00 1 0 0xA2 1010 00 1 1 0xA3 The following is an example use of the I2C master address to access an external EEPROM. The TAS3108/TAS3108IA can address up to two EEPROMs depending on the state of CS0.
Not Recommended for New Designs TAS3108, TAS3108IA AUDIO DIGITAL SIGNAL PROCESSORS www.ti.com SLES152B – OCTOBER 2005 – REVISED NOVEMBER 2007 For the standard I2C mode (SCL = 100 kHz), worst-case wait state time for an 8-MHz microprocessor clock is on the order of 2 µs. Nominal wait-state time for the same 8-MHz microprocessor clock is on the order of 1 µs. For the fast I2C mode (SCL = 400 kHz) and the same 8-MHz microprocessor clock, worst-case wait-state time can extend up to 10.5 µs in duration.
Not Recommended for New Designs TAS3108, TAS3108IA AUDIO DIGITAL SIGNAL PROCESSORS www.ti.com SLES152B – OCTOBER 2005 – REVISED NOVEMBER 2007 When the TAS3108/TAS3108IA operates as an I2C master, the TAS3108/TAS3108IA generates a repeated start without an intervening stop command while downloading program and memory data from EEPROM. When a repeated start is sent to the EEPROM in read mode, the EEPROM enters a sequential read mode to transfer large blocks of data quickly.
Not Recommended for New Designs www.ti.com TAS3108, TAS3108IA AUDIO DIGITAL SIGNAL PROCESSORS SLES152B – OCTOBER 2005 – REVISED NOVEMBER 2007 Once the microprocessor program memory has been loaded, it cannot be reloaded until the TAS3108/TAS3108IA has been reset. If an error is encountered, TAS3108/TAS3108IA terminates its memory-load operation, loads the default configuration, and disables further master I2C bus operations.
Not Recommended for New Designs TAS3108, TAS3108IA AUDIO DIGITAL SIGNAL PROCESSORS www.ti.com SLES152B – OCTOBER 2005 – REVISED NOVEMBER 2007 Table 6-5.
Not Recommended for New Designs TAS3108, TAS3108IA AUDIO DIGITAL SIGNAL PROCESSORS www.ti.com SLES152B – OCTOBER 2005 – REVISED NOVEMBER 2007 Table 6-5.
Not Recommended for New Designs TAS3108, TAS3108IA AUDIO DIGITAL SIGNAL PROCESSORS www.ti.com SLES152B – OCTOBER 2005 – REVISED NOVEMBER 2007 Table 6-5.
Not Recommended for New Designs TAS3108, TAS3108IA AUDIO DIGITAL SIGNAL PROCESSORS www.ti.com SLES152B – OCTOBER 2005 – REVISED NOVEMBER 2007 7 I2C Register Map SUBADDRESS REGISTER NAME NO. OF BYTES CONTENTS INITIALIZATION VALUE 0x00 Clock and SAP control register 4 Description shown in Section 7.1 0x01, 0x00, 0x1B, 0x22 0x01 Reserved 4 Reserved 0x00, 0x00, 0x00, 0x40 0x02 Status register 4 Description shown in Section 7.
Not Recommended for New Designs TAS3108, TAS3108IA AUDIO DIGITAL SIGNAL PROCESSORS www.ti.com SLES152B – OCTOBER 2005 – REVISED NOVEMBER 2007 7.1 Clock Control Register (0x00) Register 0x00 provides the user with control over MCLK, LRCLK, SCLKOUT1, SCLKOUT2, data-word size, and serial audio port modes. Register 0x00 default = 0x0100 1B22. Table 7-1.
Not Recommended for New Designs TAS3108, TAS3108IA AUDIO DIGITAL SIGNAL PROCESSORS www.ti.com SLES152B – OCTOBER 2005 – REVISED NOVEMBER 2007 7.1.2 Master Mode LRCLK Divider Bits 26–24 (Y2, Y1, and Y0) define the ratio between SCLK and LRCLK, but only have meaning in the clock-master mode where LRCLK is an output. In the clock-slave mode, LRCLK is an input.
Not Recommended for New Designs TAS3108, TAS3108IA AUDIO DIGITAL SIGNAL PROCESSORS www.ti.com SLES152B – OCTOBER 2005 – REVISED NOVEMBER 2007 7.1.5 Audio Data Word Size Bits 12–11 (IW1 and IW0) define the data word size for the input SAP. Bits 9–8 (OW1 and OW0) define the data word size for the output SAP. IW1/OW1 IW0/OW0 0 0 32-bit audio data 0 1 16-bit audio data 1 0 20-bit audio data 1 1 24-bit audio data 7.1.
Not Recommended for New Designs TAS3108, TAS3108IA AUDIO DIGITAL SIGNAL PROCESSORS www.ti.com SLES152B – OCTOBER 2005 – REVISED NOVEMBER 2007 7.2 Status Register (0x02) During I2C download, the write operation to indicate that a particular memory is to be written causes the TAS3108/TAS3108IA to set an error bit to indicate a load for that memory type. This error bit is cleared when the operation completes successfully. Table 7-2.
Not Recommended for New Designs TAS3108, TAS3108IA AUDIO DIGITAL SIGNAL PROCESSORS www.ti.com SLES152B – OCTOBER 2005 – REVISED NOVEMBER 2007 7.3 I2C Memory Load Control and Data Registers (0x04 and 0x05) Registers 0x04 (Table 7-3) and 0x05 (Table 7-4) allow the user to download TAS3108/TAS3108IA program code and data directly from the system I2C controller. This mode is called the I2C slave mode (from the TAS3108/TAS3108IA point-of-view).
Not Recommended for New Designs TAS3108, TAS3108IA AUDIO DIGITAL SIGNAL PROCESSORS www.ti.com SLES152B – OCTOBER 2005 – REVISED NOVEMBER 2007 7.4 Memory Access Registers (0x06 and 0x07) Registers 0x06 (Table 7-5) and 0x07 (Table 7-6) allow the user to access the internal resources of the TAS3108/TAS3108IA. See TAS3108/TAS3108IA Firmware Programmer's Guide (SLEU067) for more details. Table 7-5.
Not Recommended for New Designs TAS3108, TAS3108IA AUDIO DIGITAL SIGNAL PROCESSORS www.ti.com SLES152B – OCTOBER 2005 – REVISED NOVEMBER 2007 8 Electrical Specifications 8.1 Absolute Maximum Ratings Over Operating Temperature Range (unless otherwise noted) (1) Supply voltage range, DVDD –0.5 V to 3.8 V Supply voltage, AVDD –0.5 V to 3.8 V VI Input voltage range 3.3-V TTL VO Output voltage range 3.
Not Recommended for New Designs TAS3108, TAS3108IA AUDIO DIGITAL SIGNAL PROCESSORS www.ti.com SLES152B – OCTOBER 2005 – REVISED NOVEMBER 2007 8.
Not Recommended for New Designs TAS3108, TAS3108IA AUDIO DIGITAL SIGNAL PROCESSORS www.ti.com SLES152B – OCTOBER 2005 – REVISED NOVEMBER 2007 8.5 Timing Characteristics The following sections describe the timing characteristics of the TAS3108/TAS3108IA. 8.5.
Not Recommended for New Designs TAS3108, TAS3108IA AUDIO DIGITAL SIGNAL PROCESSORS www.ti.com SLES152B – OCTOBER 2005 – REVISED NOVEMBER 2007 8.5.2 Serial Audio Port Slave Mode Signals (TAS3108/TAS3108IA) over recommended operating conditions (unless otherwise noted) PARAMETER fLRCLK TEST CONDITIONS MIN MAX UNIT 32 (1) 192 (1) kHz 0.4 tc(SCLKIN) (1) 0.5 tc(SCLKIN) 0.
Not Recommended for New Designs TAS3108, TAS3108IA AUDIO DIGITAL SIGNAL PROCESSORS www.ti.com SLES152B – OCTOBER 2005 – REVISED NOVEMBER 2007 8.5.3 Serial Audio Port Master Mode Signals (TAS3108/TAS3108IA) over recommended operating conditions (unless otherwise noted) PARAMETER f(LRCLK) Frequency LRCLK tr(LRCLK) Rise time, LRCLK tf(LRCLK) Fall time, LRCLK TEST CONDITIONS MIN CL = 30 pF (2) (2) 32 (1) TYP MAX 192 (1) UNIT kHz CL = 30 pF 12 (1) ns Duty cycle is 50/50.
Not Recommended for New Designs TAS3108, TAS3108IA AUDIO DIGITAL SIGNAL PROCESSORS www.ti.com SLES152B – OCTOBER 2005 – REVISED NOVEMBER 2007 8.5.
Not Recommended for New Designs TAS3108, TAS3108IA AUDIO DIGITAL SIGNAL PROCESSORS www.ti.com SLES152B – OCTOBER 2005 – REVISED NOVEMBER 2007 Bus-Related Characteristics of the SDA and SCL I/O Stages for F/S-Mode I 2C-Bus Devices 8.5.5 All values are referred to VIHmin and VILmax (see Section 8.5.4). A TEST CONDITIONS PARAMETER STANDARD MODE MIN FAST MODE MAX MIN UNIT MAX fSCL SCL clock frequency (1) 0 (1) tHD-STA Hold time (repeated) START condition.
Not Recommended for New Designs TAS3108, TAS3108IA AUDIO DIGITAL SIGNAL PROCESSORS www.ti.com SLES152B – OCTOBER 2005 – REVISED NOVEMBER 2007 8.5.5.1 Recommended I2C Pullup Resistors It is recommended that the I2C pullup resistors RP be 4.7 kΩ (see Figure 8-5). If a series resistor is in the circuit (see Figure 8-6), then the series resistor RS should be less than or equal to 300 Ω. DVDD TAS3108/TAS3108IA External Microcontroller IP RP SDA SCL IP RP VI(SDA) VI(SCL) B0099-03 Figure 8-5.
Not Recommended for New Designs TAS3108, TAS3108IA AUDIO DIGITAL SIGNAL PROCESSORS www.ti.com SLES152B – OCTOBER 2005 – REVISED NOVEMBER 2007 RESET Start of Boot Sequence tw(RESET) Outputs Inactive tr(run) Enable I2C Start System T0029-02 NOTE: MCLK input = 12.288 MHz Figure 8-7.
Not Recommended for New Designs www.ti.com TAS3108, TAS3108IA AUDIO DIGITAL SIGNAL PROCESSORS SLES152B – OCTOBER 2005 – REVISED NOVEMBER 2007 9 Application Information 9.1 Schematics Figure 9-1 shows a typical TAS3108/TAS3108IA application. In this application, the following conditions apply: • • • • • • TAS3108/TAS3108IA is in clock-slave mode. The audio (SDIN1, SDIN2, SDIN3, SDIN4) and clock source (MCLKI) are external. MCLKI = 12.
Not Recommended for New Designs TAS3108, TAS3108IA AUDIO DIGITAL SIGNAL PROCESSORS www.ti.com SLES152B – OCTOBER 2005 – REVISED NOVEMBER 2007 1 0.01 µF 2 3 4 47 Ω 5 6 7 8 Audio and Clock Source 3.3 V 10 47 Ω 47 Ω 47 Ω 47 Ω 10 Ω 3.
Not Recommended for New Designs TAS3108, TAS3108IA AUDIO DIGITAL SIGNAL PROCESSORS www.ti.com SLES152B – OCTOBER 2005 – REVISED NOVEMBER 2007 9.2 Recommended Oscillator Circuit TAS3108/TAS3108IA C1 Osc Circuit rd XO C2 XI AVSS S0114-01 • • • • • MCLKI and XTLI are logically ORed together, meaning that when the XTALI pin is used, the MCLKI pin must be grounded.
PACKAGE OPTION ADDENDUM www.ti.
PACKAGE OPTION ADDENDUM www.ti.com 2-Feb-2012 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties.
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) TAS3108DCPR HTSSOP DCP 38 2000 330.0 16.4 TAS3108IADCPR HTSSOP DCP 38 2000 330.0 16.4 Pack Materials-Page 1 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 6.9 10.2 1.8 12.0 16.0 Q1 6.9 10.2 1.8 12.0 16.
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TAS3108DCPR HTSSOP DCP 38 2000 367.0 367.0 38.0 TAS3108IADCPR HTSSOP DCP 38 2000 367.0 367.0 38.
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