Datasheet

SDA
I
2
CDevice Addressand
Read/WriteBit
FirstData
Byte
Other
DataBytes
LastDataByte
Stop
Condition
Start
Condition
Acknowledge
(From
Receiver)
Acknowledge
(From
Transmitter)
Not
Acknowledge
(Transmitter)
Slave Address
Sink Port Selection Register and Source Plug-In Status Register Description (Sub-Address)
SN75DP122A
SLLS939 – NOVEMBER 2008 ............................................................................................................................................................................................ www.ti.com
address. Following this initial acknowledge by the slave, the master device becomes a receiver and
acknowledges data bytes sent by the slave. When the master has received all of the requested data bytes from
the slave, the not acknowledge (A) condition is initiated by the master by keeping the SDA signal high just before
it asserts the stop (P) condition. This sequence terminates a read cycle as shown in Figure 35 and Figure 36 .
See Example – Reading from the SN75DP122A section for more information.
Figure 35. I
2
C Read Cycle
Figure 36. Multiple Byte Read Transfer
Both SDA and SCL must be connected to a positive supply voltage via a pull-up resistor. These resistors should
comply with the I
2
C specification that ranges from 2 k Ω to 19 k Ω . When the bus is free, both lines are high. The
address byte is the first byte received following the START condition from the master device. The 7-bit address is
factory preset to 1000000. Table 2 lists the calls that the SN75DP122A responds to.
Table 2. SN75DP122A Slave Address
FIXED ADDRESS READ/WRITE BIT
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
(MSB) (R/W)
1 0 0 0 0 0 0 1
The SN75DP122A operates using a multiple byte transfer protocol similar to Figure 36 . The internal memory of
the SN75DP122A contains the phrase DP-HDMI ADAPTOR < EOT> converted to ASCII characters. The internal
memory address registers and the value of each can be found in Table 3 .
During a read cycle, the SN75DP122A sends the data in its selected sub-address in a single transfer to the
master device requesting the information. See the Example – Reading from the SN75DP122A section of this
document for the proper procedure on reading from the SN75DP122A.
Table 3. SN75DP122A Sink Port and Source Plug-In Status Registers Selection
Address 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10
Data 44 50 2D 48 44 4D 49 20 41 44 41 50 54 4F 52 04 FF
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