Datasheet
SN75ALS1177, SN75ALS1178
DUAL DIFFERENTIAL DRIVERS AND RECEIVERS
SLLS154B – MARCH 1993 – REVISED FEBRUARY 2001
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
RECEIVER SECTION
electrical characteristics over recommended ranges of common-mode input voltage, supply
voltage, and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
†
MAX UNIT
V
IT+
Positive-going input threshold voltage V
O
= 2.7 V, I
O
= –0.4 mA 0.2 V
V
IT–
Negative-going input threshold voltage V
O
= 0.5 V, I
O
= 8 mA –0.2
‡
V
V
hys
Input hysteresis voltage (V
IT+
– V
IT–
) 50 mV
V
IK
Enable input clamp voltage SN75ALS1177 I
I
= –18 mA –1.5 V
V
OH
High-level output voltage
V
ID
= 200 mV, I
OH
= –400 µA,
See Figure 2
2.7 V
V
OL
Low-level output voltage
V
ID
= 200 mV, I
OL
= 8 mA,
See Figure 2
0.45 V
I
OZ
High-impedance-state output current SN75ALS1177 V
O
= 0.4 V to 2.4 V ±20 µA
I
I
Line in
p
ut current (see Note 6)
Other in
p
ut at 0 V
V
I
= 12 V 1
mA
I
I
Line
input
current
(see
Note
6)
Other
input
at
0
V
V
I
= –7 V –0.8
mA
I
IH
High-level input current, RE SN75ALS1177 V
IH
= 2.7 V 20 µA
I
IL
Low-level input current, RE SN75ALS1177 V
IL
= 0.4 V –100 µA
r
i
Input resistance 12 kΩ
I
OS
Short-circuit output current V
O
= 0 V, See Note 7 –15 –85 mA
I
CC
Supply current (total package) No load, Outputs enabled 35 50 mA
†
All typical values are at V
CC
= 5 V and T
A
= 25°C.
‡
The algebraic convention, where the less positive (more negative) limit is designated as minimum, is used in this data sheet for common-mode
output and threshold voltage levels only.
NOTES: 6. Refer to TIA/EIA-422-B, TIA/EIA-423-A, and TIA/EIA-485-A for exact conditions.
7. Not more than one output should be shorted at a time.
switching characteristics at V
CC
= 5 V, T
A
= 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
PLH
Propagation delay time, low- to high-level output C
L
= 15 pF, See Figure 6 15 25 37 ns
t
PHL
Propagation delay time, high- to low-level output C
L
= 15 pF, See Figure 6 15 25 37 ns
t
PZH
Output enable time to high level SN75ALS1177 C
L
= 100 pF, See Figure 7 10 20 30 ns
t
PZL
Output enable time to low level SN75ALS1177 C
L
= 100 pF, See Figure 7 10 20 30 ns
t
PHZ
Output disable time from high level SN75ALS1177 C
L
= 15 pF, See Figure 7 3.5 12 16 ns
t
PLZ
Output disable time from low level SN75ALS1177 C
L
= 15 pF, See Figure 7 5 12 16 ns