Datasheet

SN74V263, SN74V273, SN74V283, SN74V293
8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FWFT mode (continued)
When configured in FWFT mode, the OR
flag output is triple register buffered, and the IR flag output is double
register buffered.
Timing diagrams for FWFT mode can be found in Figures 9, 10, and 12.
standard mode
In this mode, status flags FF
, PAF, HF, PAE, and EF operate as outlined in Table 3. To write data into to the FIFO,
WEN
must be low. Data presented to the DATA IN lines is clocked into the FIFO on subsequent transitions of
WCLK. After the first write is performed, EF
goes high after two low-to-high transitions on RCLK. Subsequent
writes continue to fill up the FIFO. PAE
goes high after n + 1 words have been loaded into the FIFO, where n
is the empty offset value. The default setting for these values is in the footnote of Table 2. This parameter also
is user programmable (see the programmable-flag offset loading section).
If one continues to write data into the FIFO and assumes no read operations are taking place, HF
switches to
low after (D/2 + 1) words are written into the FIFO. If ×18 input or ×18 output bus width is selected,
(D/2 + 1) = 4097th word for the SN74V263, 8193th word for the SN74V273, 16385th word for the SN74V283,
and 32769th word for the SN74V293. If both ×9 input and ×9 output bus widths are selected,
(D/2 + 1) = 8193rd word for the SN74V263, 16385th word for the SN74V273, 32769th word for the SN74V283,
and 65537th word for the SN74V293. Continuing to write data into the FIFO causes PAF
to go low. Again, if no
reads are performed, PAF
goes low after (D – m) writes to the FIFO. If ×8 input or ×18 output bus width is
selected, (D – m) = (8192 – m) writes for the SN74V263, (16384 – m) writes for the SN74V273, (32768 – m)
writes for the SN74V283, and (65536 – m) writes for the SN74V293. If both ×9 input and ×9 output bus widths
are selected, (D – m) = (16384 – m) writes for the SN74V263, (32768 – m) writes for the SN74V273,
(65536 – m) writes for the SN74V283, and (131072 – m) writes for the SN74V293. Offset m is the full offset
value. The default setting for these values is in the footnote of Table 2. This parameter also is user
programmable (see the programmable-flag offset loading section).
When the FIFO is full, FF
goes low, inhibiting further write operations. If no reads are performed after a reset,
FF
goes low after D writes to the FIFO. If the ×18 input or ×18 output bus width is selected, D = 8192 writes for
the SN74V263, D = 16384 writes for the SN74V273, D = 32768 writes for the SN74V283, and D = 65536 writes
for the SN74V293. If both ×9 input and ×9 output bus widths are selected, D = 16384 writes for the SN74V263,
D = 32768 writes for the SN74V273, D = 65536 writes for the SN74V283, and D = 131072 writes for the
SN74V293.
If the FIFO is full, the first read operation causes FF
to go high after two low-to-high transitions on WCLK.
Subsequent read operations cause PAF
and HF to go high at the conditions shown in Table 3. If further read
operations occur without write operations, PAE
goes low when there are n words in the FIFO, where n is the
empty offset value. Continuing read operations causes the FIFO to become empty. When the last word has been
read from the FIFO, EF
goes low, inhibiting further read operations. REN is ignored when the FIFO is empty.
When configured in standard mode, the EF
and FF outputs are double register-buffered outputs.
See Figures 7, 8, and 11 for timing diagrams for standard mode.