Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Flip-Flop Master rest Non-inverting SOIC 20

 

    

 

SCBS136M − MAY 1992 − REVISED OCTOBER 2003

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D Support Mixed-Mode Signal Operation

(5-V Input and Output Voltages With

3.3-V V

)

D Typical V

OLP

(Output Ground Bounce)

<0.8 V at V

= 3.3 V, T

= 25°C

D Support Unregulated Battery Operation

Down To 2.7 V

D Buffered Clock and Direct-Clear Inputs

D Individual Data Input to Each Flip-Flop

D I

off

Supports Partial-Power-Down-Mode

Operation

D Bus Hold on Data Inputs Eliminates the

Need for External Pullup/Pulldown

Resistors

D Latch-Up Performance Exceeds 500 mA Per

JESD 17

D ESD Protection Exceeds JESD 22

− 2000-V Human-Body Model (A114-A)

− 200-V Machine Model (A115-A)

SN54LVTH273 ...J PACKAGE

SN74LVTH273 . . . DB, DW, NS, OR PW PACKAGE

(TOP VIEW)

SN54LVTH273 . . . FK PACKAGE

(TOP VIEW)

3 2 1 20 19

9 10 11 12 13

CLR

GND

CLK

CLR

GND

CLK

description/ordering information

These octal D-type flip-flops are designed specifically for low-voltage (3.3-V) V

operation, but with the

capability to provide a TTL interface to a 5-V system environment.

The ’LVTH273 devices are positive-edge-triggered flip-flops with a direct-clear input. Information at the data (D)

inputs meeting the setup-time requirements is transferred to the Q outputs on the positive-going

edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the

transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the

D-input signal has no effect at the output.

ORDERING INFORMATION

PACKAGE

†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

SOIC − DW

Tube SN74LVTH273DW

LVTH273

SOIC − DW

Tape and reel SN74LVTH273DWR

LVTH273

−40°C to 85°C

SOP − NS Tape and reel SN74LVTH273NSR LVTH273

−40°C to 85°C

SSOP − DB Tape and reel SN74LVTH273DBR LXH273

TSSOP − PW

Tube SN74LVTH273PW

LXH273

TSSOP − PW

Tape and reel SN74LVTH273PWR

LXH273

−55°C to 125°C

CDIP − J Tube SNJ54LVTH273J SNJ54LVTH273J

−55°C to 125°C

LCCC − FK Tube SNJ54LVTH273FK SNJ54LVTH273FK

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are

available at www.ti.com/sc/package.

    !"#$%&' #"'(' 

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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Summary of content (17 pages)

PAGE 1
SCBS136M − MAY 1992 − REVISED OCTOBER 2003 D D D SN54LVTH273 . . . J PACKAGE SN74LVTH273 . . .
PAGE 2
SCBS136M − MAY 1992 − REVISED OCTOBER 2003 description/ordering information (continued) Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. These devices are fully specified for partial-power-down applications using Ioff.
PAGE 3
SCBS136M − MAY 1992 − REVISED OCTOBER 2003 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.
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SCBS136M − MAY 1992 − REVISED OCTOBER 2003 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH II = −18 mA IOH = −100 µA VCC = 2.7 V, IOH = −8 mA IOH = −24 mA VOL VCC = 3 V Data inputs Ioff VCC = 3.6 V VCC = 0, Data inputs V V 2 2 0.2 0.2 IOL = 24 mA IOL = 16 mA 0.5 0.5 0.4 0.4 IOL = 32 mA IOL = 48 mA 0.5 0.5 V 0.55 0.
PAGE 5
SCBS136M − MAY 1992 − REVISED OCTOBER 2003 switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) SN54LVTH273 PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 3.3 V ± 0.3 V MIN fmax tPLH tPHL tPHL MAX SN74LVTH273 VCC = 2.7 V MIN MAX 150 CLK Any Q CLR Any Q † All typical values are at VCC = 3.3 V, TA = 25°C. VCC = 3.3 V ± 0.3 V MIN TYP† VCC = 2.
PAGE 6
SCBS136M − MAY 1992 − REVISED OCTOBER 2003 PARAMETER MEASUREMENT INFORMATION 6V 500 Ω From Output Under Test S1 Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 6V GND 2.7 V LOAD CIRCUIT Timing Input 1.5 V 0V tw tsu 2.7 V Input 1.5 V 1.5 V th 2.7 V Data Input 1.5 V 1.5 V 0V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATION 2.7 V 1.5 V Input 1.5 V 0V VOH 1.5 V 1.
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PACKAGE OPTION ADDENDUM www.ti.
PAGE 8
PACKAGE OPTION ADDENDUM www.ti.
PAGE 9
PACKAGE OPTION ADDENDUM www.ti.
PAGE 10
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74LVTH273DBR SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1 SN74LVTH273DWR SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1 SN74LVTH273NSR SO NS 20 2000 330.0 24.4 8.2 13.0 2.5 12.0 24.
PAGE 11
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LVTH273DBR SN74LVTH273DWR SSOP DB 20 2000 367.0 367.0 38.0 SOIC DW 20 2000 367.0 367.0 45.0 SN74LVTH273NSR SO NS 20 2000 367.0 367.0 45.0 SN74LVTH273PWR TSSOP PW 20 2000 364.0 364.0 27.0 SN74LVTH273PWR TSSOP PW 20 2000 367.0 367.0 38.0 SN74LVTH273PWRG4 TSSOP PW 20 2000 367.0 367.0 38.
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MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.