Datasheet
SN74LVC1G08
SCES217W –APRIL 1999–REVISED JULY 2013
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
FUNCTION TABLE
INPUTS
OUTPUT
Y
A B
H H H
L X L
X L L
LOGIC DIAGRAM (POSITIVE LOGIC)
ABSOLUTE MAXIMUM RATINGS
(1)
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
V
CC
Supply voltage range –0.5 6.5 V
V
I
Input voltage range
(2)
–0.5 6.5 V
V
O
Voltage range applied to any output in the high-impedance or power-off state
(2)
–0.5 6.5 V
V
O
Voltage range applied to any output in the high or low state
(2)(3)
–0.5 V
CC
+ 0.5 V
I
IK
Input clamp current V
I
< 0 –50 mA
I
OK
Output clamp current V
O
< 0 –50 mA
I
O
Continuous ouput current ±50 mA
Continuous current through V
CC
or GND ±100 mA
DBV package 206
DCK package 252
θ
JA
Package thermal impedance
(4)
DRL package 142 °C/W
DRY package 234
YZP package 132
T
stg
Storage temperature range –65 150 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The value of V
CC
is provided in the recommended operating conditions table.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
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