Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Latch Transparent D latch Three-state TSSOP 20

 

   

  

SCLS407J − APRIL 1998 − REVISED APRIL 2005

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D 2-V to 5.5-V V

Operation

D Max t

of 8.5 ns at 5 V

D Typical V

OLP

(Output Ground Bounce)

<0.8 V at V

= 3.3 V, T

= 25°C

D Typical V

OHV

(Output V

Undershoot)

>2.3 V at V

= 3.3 V, T

= 25°C

D Support Mixed-Mode Voltage Operation on

All Ports

D I

off

Supports Partial-Power-Down Mode

Operation

D Latch-Up Performance Exceeds 250 mA Per

JESD 17

D ESD Protection Exceeds JESD 22

− 2000-V Human-Body Model (A114-A)

− 200-V Machine Model (A115-A)

− 1000-V Charged-Device Model (C101)

3212019

910111213

GND

SN54LV373A ...FK PACKAGE

(TOP VIEW)

SN54LV373A ...J OR W PACKAGE

SN74LV373A . . . DB, DGV, DW, NS,

OR PW PACKAGE

(TOP VIEW)

GND

SN74LV373A . . . RGY PACKAGE

(TOP VIEW)

120

10 11

GND

description/ordering information

The ’LV373A devices are octal transparent D-type latches designed for 2-V to 5.5-V V

operation.

ORDERING INFORMATION

PACKAGE

†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

QFN − RGY Reel of 1000 SN74LV373ARGYR LV373A

SOIC − DW

Tube of 25 SN74LV373ADW

LV373A

SOIC − DW

Reel of 2500 SN74LV373ADWR

LV373A

SOP − NS Reel of 2000 SN74LV373ANSR 74LV373A

−40°C to 85°C

SSOP − DB Reel of 2000 SN74LV373ADBR LV373A

−40°C to 85°C

Tube of 70 SN74LV373APW

TSSOP − PW

Reel of 2000 SN74LV373APWR

LV373A

TSSOP − PW

Reel of 250 SN74LV373APWT

LV373A

TVSOP − DGV Reel of 2000 SN74LV373ADGVR LV373A

VFBGA − GQN Reel of 1000 SN74LV373AGQNR LV373A

CDIP − J Tube of 20 SNJ54LV373AJ SNJ54LV373AJ

−55°C to 125°C

CFP − W Tube of 85 SNJ54LV373AW SNJ54LV373AW

−55 C to 125 C

LCCC − FK Tube of 55 SNJ54LV373AFK SNJ54LV373AFK

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design

guidelines are available at www.ti.com/sc/package.

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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Summary of content (25 pages)

PAGE 1
SCLS407J − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 8.5 ns at 5 V D Typical VOLP (Output Ground Bounce) D <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot) >2.3 V at VCC = 3.3 V, TA = 25°C Support Mixed-Mode Voltage Operation on All Ports 19 3 18 4 17 5 6 16 15 7 14 8 13 9 12 10 11 VCC 8Q 8D 7D 7Q 6Q 6D 5D 5Q LE 1Q 1D 2D 2Q 3Q 3D 4D 4Q 20 1D 1Q OE VCC 8Q 1 SN54LV373A .
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SCLS407J − APRIL 1998 − REVISED APRIL 2005 description/ordering information (continued) While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low) or the high-impedance state.
PAGE 3
SCLS407J − APRIL 1998 − REVISED APRIL 2005 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.
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SCLS407J − APRIL 1998 − REVISED APRIL 2005 recommended operating conditions (see Note 5) SN54LV373A VCC VIH Supply voltage High-level input voltage VIL Low-level input voltage VI Input voltage VO Output voltage IOH IOL ∆t/∆v VCC = 2 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V MIN MAX 2 5.5 2 5.5 VCC × 0.7 VCC × 0.7 VCC × 0.7 VCC × 0.7 VCC × 0.7 VCC × 0.
PAGE 5
SCLS407J − APRIL 1998 − REVISED APRIL 2005 timing requirements over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1) TA = 25°C MIN MAX SN54LV373A MIN MAX SN74LV373A MIN MAX UNIT tw Pulse duration, LE high 6 6.5 6.5 ns tsu Setup time, data before LE↓ High or low 4.5 5 5 ns th Hold time, data after LE↓ High or low 1.5 1.5 1.
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SCLS407J − APRIL 1998 − REVISED APRIL 2005 switching characteristics over recommended operating VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE MIN free-air TA = 25°C TYP MAX temperature SN54LV373A range, SN74LV373A MIN MAX MIN MAX 13.5 D Q 5.8* 11.4* 1* 13.5* 1 LE Q 6.4* 11* 1* 13* 1 13 ten OE Q 6.3* 11.4* 1* 13.5* 1 13.5 tdis OE Q 4.
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SCLS407J − APRIL 1998 − REVISED APRIL 2005 PARAMETER MEASUREMENT INFORMATION From Output Under Test RL = 1 kΩ From Output Under Test Test Point S1 VCC Open TEST GND CL (see Note A) CL (see Note A) S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain Open VCC GND VCC LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS VCC 50% VCC Timing Input tw tsu VCC 50% VCC Input 50% VCC 0V th VCC 50% VCC Data I
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PACKAGE OPTION ADDENDUM www.ti.
PAGE 9
PACKAGE OPTION ADDENDUM www.ti.
PAGE 10
PACKAGE OPTION ADDENDUM www.ti.com 18-Oct-2013 Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.
PAGE 11
PACKAGE MATERIALS INFORMATION www.ti.com 8-Jul-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 7.5 2.5 12.0 16.0 Q1 SN74LV373ADBR SSOP DB 20 2000 330.0 16.4 SN74LV373ADGVR TVSOP DGV 20 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74LV373ADWR SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.
PAGE 12
PACKAGE MATERIALS INFORMATION www.ti.com 8-Jul-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LV373ADBR SSOP DB 20 2000 367.0 367.0 38.0 SN74LV373ADGVR TVSOP DGV 20 2000 367.0 367.0 35.0 SN74LV373ADWR SOIC DW 20 2000 367.0 367.0 45.0 SN74LV373ANSR SO NS 20 2000 367.0 367.0 45.0 SN74LV373APWR TSSOP PW 20 2000 364.0 364.0 27.0 SN74LV373APWR TSSOP PW 20 2000 367.0 367.0 38.
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MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,40 0,23 0,13 24 13 0,07 M 0,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 0°– 8° 1 0,75 0,50 12 A Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,08 14 16 20 24 38 48 56 A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 DIM 4073251/E 08/00 NOTES: A. B. C. D. All linear dimensions are in millimeters.
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MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.