Datasheet

SN54LV164A, SN74LV164A
8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS
SCLS403H − APRIL 1998 − REVISED APRIL 2005
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description/ordering information (continued)
These devices feature AND-gated serial (A and B) inputs and an asynchronous clear (CLR) input. The gated
serial inputs permit complete control over incoming data, as a low at either input inhibits entry of the new data
and resets the first flip-flop to the low level at the next clock pulse. A high-level input enables the other input,
which then determines the state of the first flip-flop. Data at the serial inputs can be changed while the clock
is high or low, provided the minimum setup time requirements are met. Clocking occurs on the low-to-high-level
transition of the clock (CLK) input.
FUNCTION TABLE
INPUTS
OUTPUTS
CLR CLK A B Q
A
Q
B
...Q
H
L X X X L L L
H LXXQ
A0
Q
B0
Q
H0
H ↑ HHHQ
An
Q
Gn
H ↑ LXLQ
An
Q
Gn
H ↑ X L L Q
An
Q
Gn
Q
A0
, Q
B0
, Q
H0
= the level of Q
A
, Q
B
, or Q
H
, respectively,
before the indicated steady-state input conditions were
established.
Q
An
, Q
Gn
= the level of Q
A
or Q
G
before the most recent
↑ transition of the clock: indicates a 1-bit shift.
logic diagram (positive logic)
C1
1D
R
C1
1D
R
Q
A
Q
B
C1
1D
R
C1
1D
R
Q
C
Q
D
C1
1D
R
C1
1D
R
Q
E
Q
F
C1
1D
R
C1
1D
R
Q
G
Q
H
345610111213
8
1
2
9
CLK
A
B
CLR
Pin numbers shown are for the D, DB, DGV, J, NS, PW, RGY, and W packages.