Datasheet

5-3
FAST AND LS TTL DATA
SN54/74LS175
AC CHARACTERISTICS (T
A
= 25°C)
Sbl
P
Limits
Ui
T C di i
Symbol Parameter
Min Typ Max
Unit Test Conditions
f
MAX
Maximum Input Clock Frequency 30 40 MHz
V50V
t
PLH
t
PHL
Propagation Delay, MR to Output
20
20
30
30
ns
V
CC
= 5.0 V
C
L
= 15
p
F
t
PLH
t
PHL
Propagation Delay, Clock to Output
13
16
25
25
ns
C
L
=
15
pF
AC SETUP REQUIREMENTS (T
A
= 25°C)
Sbl
P
Limits
Ui
T C di i
Symbol Parameter
Min Typ Max
Unit Test Conditions
t
W
Clock or MR Pulse Width 20 ns
V50V
t
s
Data Setup Time 20 ns
V
CC
=50V
t
h
Data Hold Time 5.0 ns
V
CC
=
5
.
0
V
t
rec
Recovery Time 25 ns
AC WAVEFORMS
Figure 1. Clock to Output Delays, Clock Pulse Width,
Frequency, Setup and Hold Times Data to Clock
Figure 2. Master Reset to Output Delay, Master Reset
Pulse Width, and Master Reset Recovery Time
1.3 V
1.3 V 1.3 V
Q
Q
t
PLH
t
PLH
t
PHL
1.3 V
*The shaded areas indicate when the input is permitted to
*change for predictable output performance.
1.3 V
1.3 V 1.3 V
1.3 V 1.3 V
1.3 V
1.3 V
1.3 V
1.3 V1.3 V
1/f
max
t
w
t
s(H)
t
h(H)
t
s(L)
t
h(L)
CP
t
PHL
t
PLH
t
W
t
PHL
CP
t
rec
Q
MR
D
Q
*
1.3 V
1.3 V
DEFINITIONS OF TERMS
SETUP TIME (t
s
) — is defined as the minimum time required
for the correct logic level to be present at the logic input prior to
the clock transition from LOW to HIGH in order to be recog-
nized and transferred to the outputs.
HOLD TIME (t
h
) — is defined as the minimum time following
the clock transition from LOW to HIGH that the logic level must
be maintained at the input in order to ensure continued recog-
nition. A negative HOLD TIME indicates that the correct logic
level may be released prior to the clock transition from LOW to
HIGH and still be recognized.
RECOVERY TIME (t
rec
) — is defined as the minimum time
required between the end of the reset pulse and the clock
transition from LOW to HIGH in order to recognize and transfer
HIGH Data to the Q outputs.