Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Latch Transparent D latch Three-state PDIP 20

SN54HCT573, SN74HCT573

OCTAL TRANSPARENT D-TYPE LATCHES

WITH 3-STATE OUTPUTS

SCLS176E – MARCH 1984 – REVISED JULY 2003

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Operating Voltage Range of 4.5 V to 5.5 V

High-Current 3-State Outputs Drive Bus

Lines Directly or Up To 15 LSTTL Loads

Low Power Consumption, 80-µA Max I

Typical t

= 21 ns

±6-mA Output Drive at 5 V

Low Input Current of 1 µA Max

Inputs Are TTL-Voltage Compatible

Bus-Structured Pinout

description/ordering information

These octal transparent D-type latches feature

3-state outputs designed specifically for driving

highly capacitive or relatively low-impedance

loads. The ’HCT573 devices are particularly

suitable for implementing buffer registers, I/O

ports, bidirectional bus drivers, and working

registers.

While the latch-enable (LE) input is high, the

Q outputs respond to the data (D) inputs. When

LE is low, the outputs are latched to retain the data

that was set up at the D inputs.

A buffered output-enable (OE

) input can be used

to place the eight outputs in either a normal logic

state (high or low logic levels) or the

high-impedance state. In the high-impedance

state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased

drive provide the capability to drive bus lines without interface or pullup components.

ORDERING INFORMATION

PACKAGE

†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

PDIP – N Tube SN74HCT573N SN74HCT573N

SOIC DW

Tube SN74HCT573DW

HCT573

SOIC

–

Tape and reel SN74HCT573DWR

HCT573

–40°C to 85°C

SOP – NS Tape and reel SN74HCT573NSR HCT573

SSOP – DB Tape and reel SN74HCT573DBR HT573

TSSOP PW

Tube SN74HCT573PW

HT573

TSSOP

–

Tape and reel SN74HCT573PWR

HT573

CDIP – J Tube SNJ54HCT573J SNJ54HCT573J

–55°C to 125°C

CFP – W Tube SNJ54HCT573W SNJ54HCT573W

LCCC – FK Tube SNJ54HCT573FK SNJ54HCT573FK

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are

available at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

3212019

910111213

GND

SN54HCT573 . . . FK PACKAGE

(TOP VIEW)

SN54HCT573 ...J OR W PACKAGE

SN74HCT573 . . . DB, DW, N, NS, OR PW PACKAGE

(TOP VIEW)

GND

UNLESS OTHERWISE NOTED this document contains PRODUCTION

DATA information current as of publication date. Products conform to

specifications per the terms of Texas Instruments standard warranty.

Production processing does not necessarily include testing of all

parameters.

Summary of content (17 pages)

PAGE 1
SN54HCT573, SN74HCT573 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCLS176E – MARCH 1984 – REVISED JULY 2003 D D D D D D SN54HCT573 . . . J OR W PACKAGE SN74HCT573 . . . DB, DW, N, NS, OR PW PACKAGE (TOP VIEW) Operating Voltage Range of 4.5 V to 5.
PAGE 2
SN54HCT573, SN74HCT573 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCLS176E – MARCH 1984 – REVISED JULY 2003 description/ordering information (continued) OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
PAGE 3
SN54HCT573, SN74HCT573 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCLS176E – MARCH 1984 – REVISED JULY 2003 recommended operating conditions (see Note 3) SN54HCT573 NOM MAX MIN NOM MAX 4.5 5 5.5 4.5 5 5.5 VCC VIH Supply voltage VIL VI Low-level input voltage Input voltage 0 VO ∆t/∆v Output voltage 0 High-level input voltage SN74HCT573 MIN VCC = 4.5 V to 5.5 V VCC = 4.5 V to 5.5 V 2 2 Input transition rise/fall time V V 0.8 VCC VCC UNIT 0 0 500 0.
PAGE 4
SN54HCT573, SN74HCT573 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCLS176E – MARCH 1984 – REVISED JULY 2003 switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) D Q tpd d LE Any Q ten OE Any Q tdis di OE Any Q tt Any Q VCC MIN TA = 25°C TYP MAX SN54HCT573 MIN MAX SN74HCT573 MIN MAX 4.5 V 25 35 53 44 5.5 V 21 32 48 40 4.5 V 28 35 53 44 5.
PAGE 5
SN54HCT573, SN74HCT573 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCLS176E – MARCH 1984 – REVISED JULY 2003 PARAMETER MEASUREMENT INFORMATION VCC S1 Test Point From Output Under Test PARAMETER ten RL tdis CL (see Note A) S2 tPZH RL 1 kΩ tPZL tPHZ tPLZ tpd or tt 1 kΩ CL S1 S2 50 pF or 150 pF Open Closed Closed Open Open Closed Closed Open Open Open 50 pF 50 pF or 150 pF –– LOAD CIRCUIT 3V High-Level Pulse 1.3 V 3V Reference Input 1.3 V 0V 1.
PAGE 6
PACKAGE OPTION ADDENDUM www.ti.
PAGE 7
PACKAGE OPTION ADDENDUM www.ti.com 18-Sep-2008 http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials.
PAGE 8
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74HCT573DBR SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1 SN74HCT573DWR SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1 SN74HCT573NSR SO NS 20 2000 330.0 24.4 8.2 13.0 2.5 12.0 24.
PAGE 9
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74HCT573DBR SN74HCT573DWR SSOP DB 20 2000 367.0 367.0 38.0 SOIC DW 20 2000 367.0 367.0 45.0 SN74HCT573NSR SO NS 20 2000 367.0 367.0 45.0 SN74HCT573PWR TSSOP PW 20 2000 367.0 367.0 38.
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MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters.
PAGE 17
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.