Datasheet

SN74F161A
SYNCHRONOUS 4-BIT BINARY COUNTER
SDFS056B – MARCH 1987 – REVISED AUGUST 2001
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
typical clear, preset, count, and inhibit sequences
The following timing sequence is illustrated below:
1. Clear outputs to zero
2. Preset to binary 12
3. Count to 13, 14, 15, 0, 1, and 2
4. Inhibit
Data
Inputs
Data
Outputs
CLR
LOAD
A
B
C
D
CLK
ENP
ENT
RCO
Q
A
Q
B
Q
C
Q
D
Async
Clear
Sync
Clear
Preset
Count Inhibit
12 13
14 15 0 1 2