Datasheet


   
       
SCDS159B − OCTOBER 2003 − REVISED MARCH 2004
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
1A1
SW
1B1
1A5
1OE
SW
1B5
2A1
SW
2B1
2A5
2OE
SW
2B5
3
11
1
14
22
13
2
10
15
23
simplified schematic, each FET switch (SW)
V
G
†
A
EN
‡
B
†
Gate Voltage (V
G
) is approximately
equal to V
CC
+ V
T
when the switch is ON
and V
I
> V
CC
+ V
T
.
Control
Circuit
‡
EN is the internal enable signal applied to the switch.