Datasheet

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APPLICATION INFORMATION
1
2
3
6
5
4
V
CC1
V
CC1
V
CC2
SYSTEM-1 SYSTEM-2
DIR CTRL
I/O-1 I/O-2
V
CC2
STATE DIR CTRL I/O-1 DESCRIPTION
1
2
3
4
H
H
L
L
Out
Hi−Z
SYSTEM-1 data to SYSTEM-2
SYSTEM-2 is getting ready to send data to SYSTEM-1. I/O-1
and I/O-2 are disabled. The bus-line state depends on bus hold.
DIR bit is flipped. I/O-1 and I/O02 still are disabled. The bus-line
state depends on bus hold.
I/O-2
Hi−Z
Out
In
Hi−Z
Hi−Z
In SYSTEM-2 data to SYSTEM-1
Enable Times
SN74AVCH1T45
SINGLE-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
SCES598D – JULY 2004 – REVISED JANUARY 2008
Figure 13 shows the SN74AVCH1T45 being used in a bidirectional logic level-shifting application. Since the
SN74AVCH1T45 does not have an output-enable (OE) pin, the system designer should take precautions to avoid
bus contention between SYSTEM-1 and SYSTEM-2 when changing directions.
Figure 13. Bidirectional Logic Level-Shifting Application
Following is a sequence that illustrates data transmission from SYSTEM-1 to SYSTEM-2 and then from
SYSTEM-2 to SYSTEM-1.
Calculate the enable times for the SN74AVCH1T45 using the following formulas:
• t
PZH
(DIR to A) = t
PLZ
(DIR to B) + t
PLH
(B to A)
• t
PZL
(DIR to A) = t
PHZ
(DIR to B) + t
PHL
(B to A)
• t
PZH
(DIR to B) = t
PLZ
(DIR to A) + t
PLH
(A to B)
• t
PZL
(DIR to B) = t
PHZ
(DIR to A) + t
PHL
(A to B)
In a bidirectional application, these enable times provide the maximum delay from the time the DIR bit is
switched until an output is expected. For example, if the SN74AVCH1T45 initially is transmitting from A to B, then
the DIR bit is switched; the B port of the device must be disabled before presenting it with an input. After the B
port has been disabled, an input signal applied to it appears on the corresponding A port after the specified
propagation delay.
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